Agilex™ 7 Power Distribution Network Design Guidelines

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ID 683393
Date 10/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Agilex™ 7 Device Family PDN Design Summary 9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Agilex™ 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Agilex™ 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines

2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary

Table 15.   Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile
Agilex™ 7 PTC Rail Name Bottom-side Capacitors FPGA Periphery Capacitors Notes
Thick PCB (≥65 mil thickness) Thin PCB (≤65 mil thickness) Thick PCB (≥65 mil thickness) Thin PCB (≤65 mil thickness)
VCCRT_GXE 6x 4.7uF 0201 6x 4.7uF 0201 LC filter capacitors LC filter capacitors

Per each E-Tile.

This is applicable to both reasonable worst case and low power scenario case. For the low power scenario case, the maximum current is 3 A, and the difference is the LC filter capacitors.

For more information, refer to the Connection Requirement and Filter Recommendation for VCCRT_GXE per Tile and Connection Requirement and Filter Recommendation for VCCRT_GXE per Tile (Low Power Scenario) figures.

VCCRTPLL_GXE 2x 1uF 0201 2x 1uF 0201 LC filter capacitors LC filter capacitors Per each E-Tile
VCC_HSSI_GXE

3x 10uF 0402 or 10x 4.7uF 0201

3x 10uF 0402 or 10x 4.7uF 0201

 N/A N/A Per each E-Tile
VCCH_GXE 2x 4.7uF 0201 2x 4.7uF 0201 1x 22uF 0603 1x 22uF 0603 Per each E-Tile
VCCCLK_GXE 1x 1uF 0201 1x 1uF 0201 N/A N/A Per each E-Tile

Although it is not required to use the recommended decoupling capacitors and LC filters for unused E-Tile, Altera recommends you to use at least one of each suggested decoupling capacitors for the bottom-side capacitors if the E-Tile is not used.

If you plan to run the E-Tile based on OTN protocol standards, contact Intel® Premier Support and quote ID #1509475736 to receive a step-by-step guideline about updating or adjusting the PCB decoupling capacitors for E-Tile (only for VCCRT_GXE and VCCRTPLL_GXE power rails) to support the OTN application.

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