Agilex™ 7 Power Distribution Network Design Guidelines

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ID 683393
Date 10/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Agilex™ 7 Device Family PDN Design Summary 9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Agilex™ 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Agilex™ 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines

2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary

The Agilex™ 7 FPGA F-Series, I-Series, and M-Series Decoupling Capacitors Summary table shows the PCB recommended FPGA decoupling capacitor requirement for the Agilex™ 7 AGF006/AGF008 (small package size), Agilex™ 7 AGF012/AGF014 (medium package size), Agilex™ 7 AGI041/AGI040/AGI035/AGI027/AGI023/AGI022/AGI019, Agilex™ 7 AGF027/AGF023/AGF022/AGF019, and Agilex™ 7 AGM039/AGM032 large device packages.

Fabric or core decoupling capacitors are highly dependent on the size of the core or fabric (LE and number of GPIO pins) in the package.

Decoupling capacitor recommendations for each tile is valid for any size of packages.

Table 14.   Agilex™ 7 FPGA F-Series, I-Series, and M-Series Decoupling Capacitors Summary
Device Agilex™ 7 Power and Thermal Calculator (PTC) Rail Name Bottom-side Capacitors FPGA Periphery Capacitors Notes
Thick PCB (>65 mil thickness) Thin PCB (≤65 mil thickness) Thick PCB (>65 mil thickness) Thin PCB (≤65 mil thickness)
FPGA AGF006/AGF008 (R16A and R24B) Fabric Merged VCC and VCCP 3x 47uF 0805 3x 47uF 0805 3x 47uF 0805 3x 47uF 0805

VR vendors capacitors recommendation must be compiled.

Place 47uF 0805 capacitors inside bottom-side cavity.

Use 47uF 0805 periphery capacitors on top-layer near FPGA.

FPGA AGF012/AGF014 (R24B and R24C) Fabric Merged VCC and VCCP

9x 47uF 0805

30x 10uF 0402 DNI 8

5x 47uF 0805

30x 10uF 0402 DNI8

6x 47uF 0805

 3x 47uF 0805

VR vendors capacitors recommendation must be compiled.

Place thick 0805 (47uF) capacitors inside bottom-side cavity.

Use 47uF 0805 periphery capacitors on top-layer near FPGA.

Place 0402 capacitors in the FPGA pin field.

FPGA AGF012/AGF014 (R24B and R24C) Fabric Merged VCC and VCCP (low power scenario) N/A

2x 100uF 0805

4x 47uF 0805

20x 10uF 0402 DNI8

N/A N/A

For the low power scenario case, the maximum current is at 70 A. Thin board only for PCIe* FF.

You must comply with the capacitors recommendation provided by the voltage regulators vendors.

Place thick 0805 (47uF and 100uF) capacitors inside the bottom-side cavity. Place 0402 capacitors in the FPGA pin field.

FPGA AGF019/AGF023 Fabric (R25A, R24C, R31C) and AGI019/AGI023 (R31B, R18A) Fabric Merged VCC and VCCP

6x 100uF 0805

6x 47uF 0805

30x 10uF 0402 DNI8

4x 100uF 0805

4x 47uF 0805

20x 10uF 0402 DNI8

6x 100uF 0805

6x 47uF 0805

4x 100uF 0805

4x 47uF 0805

VR vendors capacitors recommendation must be compiled.

Place thick 0805 (47uF and 100uF) capacitors inside bottom-side cavity.

Use 47uF and 100uF 0805 periphery capacitors on top-layer near FPGA.

Place 0402 capacitors in the FPGA pin field.

FPGA AGF022/AGF027 Fabric (R25A, R24C, R31C) and AGI022/AGI027 (R29A, R31A, R31B )Fabric Merged VCC and VCCP

8x 100uF 0805

4x 47uF 0805

40x 10uF 0402 DNI8

6x 100uF 0805

4x 47uF 0805

30x 10uF 0402 DNI8

12x 100uF 0805

10x 47uF 0805

10x 100uF 0805

8x 47uF 0805

VR vendors capacitors recommendation must be compiled.

Place thick 0805 (47uF and 100uF) capacitors inside bottom-side cavity.

Use 47uF and 100uF 0805 periphery capacitors on top-layer near FPGA.

Place 0402 capacitors in the FPGA pin field.

FPGA AGI035/AGI040 (R39A) Fabric Merged VCC and VCCP

14x 100uF 0805

50x 10uF 0402 DNI8

10x 100uF 0805

50x 10uF 0402 DNI8

24x 100uF 0805

 20x 100uF 0805

VR vendors capacitors recommendation must be compiled.

Place thick 0805 (100uF) capacitors inside bottom-side cavity.

Use 100uF 0805 periphery capacitors on top-layer near FPGA.

Place 0402 capacitors in the FPGA pin field.

FPGA AGI041 (R29D, R31B, R31E) Fabric Merged VCC and VCCP

19x 100uF 0805

50x 10uF 0402 DNI8

15x 100uF 0805

30x 10uF 0402 DNI8

17x 100uF 0805

13x 100uF 0805

VR vendors capacitors recommendation must be compiled.

Place thick 0805 (100uF) capacitors inside bottom-side cavity.

Use 100uF 0805 periphery capacitors on top-layer near FPGA.

Place 0402 capacitors in the FPGA pin field.

FPGA AGM039/AGM032 (R47A) Fabric Merged VCC and VCCP

18x 100uF 0805

50x 10uF 0402 DNI8

15x 100uF 0805

30x 10uF 0402 DNI8

55x 100uF 0805

50x 100uF 0805

VR vendors capacitors recommendation must be compiled.

Place thick 0805 (100uF) capacitors inside bottom-side cavity.

Use 100uF 0805 periphery capacitors on top-layer near FPGA.

Place 0402 capacitors in the FPGA pin field.

FPGA AGM039 (R31B) Fabric Merged VCC and VCCP

10x 100uF 0805

30x 10uF 0402 DNI8

10x 100uF 0805

30x 10uF 0402 DNI8

40x 100uF 0805

40x 100uF 0805

VR vendors capacitors recommendation must be compiled.

Place thick 0805 (100uF) capacitors inside bottom-side cavity.

Use 100uF 0805 periphery capacitors on top-layer near FPGA.

Place 0402 capacitors in the FPGA pin field.

FPGA AGI, AGF, and AGM/HPS VCCPLLDIG_HPS 1x 1uF 0201 1x 1uF 0201 LC filter capacitors LC filter capacitors —
FPGA AGI, AGF, and AGM/HPS VCCL_HPS

2x 10uF 0402 or 3x 4.7uF 0201

2x 10uF 0402 or 3x 4.7uF 0201

1x 22uF 0603

1x 22uF 0603

 For SoC-centric designs.
FPGA AGI, AGF, and AGM VCCH

4x 22uF 0603

4x 22uF 0603

 2x 47uF 0805 2x 47uF 0805 Place thick 0603 (22uF) capacitors inside bottom-side cavity.
FPGA AGI, AGF, and AGM/SDM VCCH_SDM 1x 1uF 0201 1x 1uF 0201 N/A N/A —
FPGA AGI, AGF, and AGM/SDM VCCL_SDM 2x 1uF 0201 2x 1uF 0201 N/A N/A —
FPGA AGI, AGF, and AGM/SDM VCCPLLDIG_SDM 1x 1uF 0201 1x 1uF 0201 LC filter capacitors LC filter capacitors —
FPGA AGI, AGF, and AGM VCCPT 2x 4.7uF 0201 2x 4.7uF 0201 N/A N/A  
FPGA AGI, AGF, and AGM/PIO VCCRCORE 1x 1uF 0201 1x 1uF 0201 N/A N/A —
FPGA AGI, AGF, and AGM/PIO VCCA_PLL 2x 10uF 0402 2x 10uF 0402 LC filter capacitors LC filter capacitors This is applicable to both reasonable worst case and low power scenario case. For the low power scenario case, the maximum current is 1 A, and the difference is the LC filter capacitors. For more information, refer to the VCCA_PLL Filter Recommendation and VCCA_PLL LC Filter Recommendation (Low Power Scenario) figures.
FPGA AGI, AGF, and AGM/SDM VCCADC 1x 1uF 0201 1x 1uF 0201 LC filter capacitors LC filter capacitors —
FPGA AGI, AGF, and AGM/SDM VCCPLL_SDM 1x 1uF 0201 1x 1uF 0201 LC filter capacitors LC filter capacitors —
FPGA AGI, AGF, and AGM/HPS VCCPLL_HPS 1x 1uF 0201 1x 1uF 0201 LC filter capacitors LC filter capacitors —
FPGA AGI, AGF, and AGM/SDM VCCIO_PIO_SDM 1x 1uF 0201 1x 1uF 0201 N/A N/A —
FPGA AGI, AGF, and AGM/PIO VCCIO_PIO 2x 4.7uF 0402 2x 4.7uF 0402 1x 10uF 0402 1x 10uF 0402 Per each I/O bank
FPGA AGI, AGF, and AGM/SDM VCCIO_SDM 1x 1uF 0201 1x 1uF 0201 1x 10uF 0402 1x 10uF 0402 —
FPGA AGI, AGF, and AGM/HPS VCCIO_HPS 1x 1uF 0201 1x 1uF 0201 N/A N/A —
FPGA AGI, AGF, and AGM/SDM VCCBAT 1x 1uF 0201 1x 1uF 0201 1x 10uF 0402 1x 10uF 0402 —
FPGA AGI, AGF, and AGM/SDM VCCFUSEWR_SDM 1x 1uF 0201 1x 1uF 0201 1x 4,7uF 0201 1x 4,7uF 0201 —
FPGA AGM/UIB VCCIO_UIB 1x 10uF 0402 1x 10uF 0402 2x 47uF 0805 2x 47uF 0805 Per HBM
FPGA AGM/UIB VCCM_PUMP_HBM 1x 10uF 0402 1x 10uF 0402 N/A N/A Per HBM
FPGA AGM/NOC VCCIO_NOC 1x 1uF 0402 1x 1uF 0402 N/A N/A Per side
FPGA AGM/NOC VCCPLL_NOC 1x 2.2uF 0402 1x 2.2uF 0402 LC filter capacitors LC filter capacitors Per side
FPGA AGM/NOC VCCLPLL_NOC 1x 2.2uF 0402 1x 2.2uF 0402 LC filter capacitors LC filter capacitors Per side
FPGA AGM/NOC VCCPLLDIG_NOC 1x 2.2uF 0402 1x 2.2uF 0402 LC filter capacitors LC filter capacitors Per side
8 DNI: Do not install these capacitors but include the footprints of these capacitors. This is for defensive design for additional decoupling capacitance in the event the cavity capacitor (0805) is not sufficient.
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