Agilex™ 7 Power Distribution Network Design Guidelines

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ID 683393
Date 10/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Agilex™ 7 Device Family PDN Design Summary 9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Agilex™ 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Agilex™ 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines

2.2. Rail Merger Requirements

IP voltage rails of same nominal values within the same sequencing group can be merged assuming that the power delivery network to each package balls for each IP is designed with care to meet the tolerance specifications of that IP. Therefore, proper analysis or simulations should be done to ensure voltage drop and cross regulations are under control.

As many power rails are merged on the motherboard, the requirement for an LC filter is necessary to ensure systems functionality especially for rail connections to sensitive circuits such as the phase-locked loop (PLL) and clock. Altera recommends you to follow the LC filter requirements.

For more information about the rail merger requirements, refer to the Agilex™ 7 Device Family Pin Connection Guidelines.

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