Agilex™ 7 Power Distribution Network Design Guidelines

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ID 683393
Date 10/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Agilex™ 7 Device Family PDN Design Summary 9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Agilex™ 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Agilex™ 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines

2.3.1.1. Agilex™ 7 Package Power Nets and Subsystems Details

Table 4.   Agilex™ 7 AGF (with only E-Tile and P-Tile), Agilex™ 7 AGF (with only F-Tile), and Agilex™ 7 AGI (with only F-Tile, or both F-Tile and R-Tile) FPGA Package Power Rail Nets and Subsystem Details
Device Power Thermal Calculator (PTC) Rail Name Board Connections System Connections
FPGA VCC VCCL 0.8 V Fabric core
FPGA/HPS VCCL_HPS HPS core for –1, –2, and –3 devices. Refer to the notes in the Recommended Agilex™ 7 AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices and Recommended Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon figures.
FPGA/HPS VCCPLLDIG_HPS HPS core for –1, –2, and –3 devices. Refer to the notes in the Recommended Agilex™ 7 AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices and Recommended Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon figures.
FPGA/PIO VCCP I/O 96 PHY
FPGA packages with E-Tile and P-Tile VCCH VCCH 0.9 V/P0V9_GR1 Rail for AIB-Bridge for FPGA packages with E-Tile and P-Tiles.
FPGA/SDM VCCH_SDM SDM POR monitoring ball for VCCH of FPGA packages (with E-Tile and P-Tile) or FPGA packages (with F-Tile and R-Tile).
FPGA packages (with F-Tile and R-Tile) or packages (with F-Tile only) VCCH P0V8_GR1 Rail for AIB-Bridge for packages with F-Tile and R-Tile or packages with F-Tile only.
FPGA/SDM VCCH_SDM SDM POR monitoring ball for VCCH of FPGA packages (with F-Tile only).
FPGA/SDM VCCL_SDM SDM core
FPGA/SDM VCCPLLDIG_SDM SDM digital PLL
FPGA VCCPT P1V8_GR2 CRAM
FPGA/SDM VCCADC ADC
FPGA/SDM VCCPLL_SDM SDM analog PLL
FPGA/HPS VCCPLL_HPS HPS analog PLL
FPGA/SDM VCCIO_PIO_SDM P1V2_GR3 SDM POR monitor for VCCIO_PIO_SDM
FPGA/PIO VCCIO_PIO I/O 96 I/O buffer
FPGA VCCRCORE Share with VCCIO_PIO only when I/O is 1.2 V.
FPGA VCCA_PLL Main DDR PLL
FPGA/SDM VCCIO_SDM P1V8_GR3 SDM 1.8 V I/O supply
FPGA/HPS VCCIO_HPS HPS I/O supply
FPGA/SDM VCCBAT VCCBAT Battery back-up power supply for device security Advanced Encryption Standard, Battery-backed RAM (AES BBRAM) key register.
FPGA/SDM VCCFUSEWR_SDM VCCFUSEWR_SDM

SDM fuse.

Fuse programming is only allowed when there is no activity on the I/O rail, VCCIO_SDM, and VCCIO_HPS.

Otherwise, a separate power module is required for VCCFUSEWR_SDM.

Table 5.   Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) FPGA Package Power Rail Nets and Subsystem Details
Device Power Thermal Calculator (PTC) Rail Name Board Connections System Connections
FPGA VCC VCCL 0.8 V Core fabric
FPGA/HPS VCCL_HPS HPS core for –1, –2, and –3 devices. Refer to the notes in the Recommended Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Engineering Sample (ES) Silicon figure.
FPGA/HPS VCCPLLDIG_HPS HPS core for –1, –2, and –3 devices. Refer to the notes in the Recommended Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Engineering Sample (ES) Silicon figure.
FPGA/PIO VCCP I/O 96 PHY
FPGA/SDM VCCH_SDM VCC_HSSI_GXR Must connect this sense to the VCC_HSSI_GXR rail for the Agilex™ 7 devices with both F-Tile and R-Tile.
FPGA packages (with F-Tile and R-Tile) or FPGA packages (with F-Tile only) VCCH P0V8_GR1 Rail for AIB-Bridge for packages with F-Tile and R-Tile or packages with F-Tile only.
FPGA/SDM VCCH_SDM SDM POR monitoring ball for VCCH of FPGA packages (with F-Tile only).
FPGA/SDM VCCL_SDM SDM core
FPGA/SDM VCCPLLDIG_SDM SDM digital PLL
FPGA/NOC VCCLPLL_NOC I/O and digital power pin for network-on-chip
FPGA/NOC VCCPLLDIG_NOC Digital power pin for network-on-chip
FPGA/UIB VCCM_PUMP_HBM VCCM_PUMP_HBM 2.5 V Pump power supply for HBM2E
FPGA VCCPT P1V8_GR3/Group 3a CRAM
FPGA/NOC VCCIO_NOC I/O power pin for network-on-chip
FPGA/SDM VCCADC ADC
FPGA/SDM VCCPLL_SDM SDM analog PLL
FPGA/HPS VCCPLL_HPS HPS analog PLL
FPGA/NOC VCCPLL_NOC Analog power pin for network-on-chip
FPGA/SDM VCCIO_SDM SDM 1.8 V I/O supply
FPGA/HPS VCCIO_HPS HPS I/O supply
FPGA/SDM VCCFUSEWR_SDM SDM fuse
FPGA/SDM VCCIO_PIO_SDM P1V2_GR3/Group 3b SDM POR monitor for VCCIO_PIO_SDM
FPGA/PIO VCCIO_PIO I/O 96 I/O buffer
FPGA/UIB VCCIO_UIB I/O power supply for UIB
FPGA VCCRCORE Share with VCCIO_PIO when I/O is 1.2 V.
FPGA/SDM VCCBAT VCCBAT Battery back-up power supply for device security Advanced Encryption Standard, Battery-backed RAM (AES BBRAM) key register.
Table 6.   Agilex™ 7 E-Tile Power Rail Nets and Subsystem Details
PTC Rail Name Board Connections System Connections
VCCRT_GXE VCCH 0.9 V E-Tile TX/RX transceiver analog
VCCRTPLL_GXE E-Tile TX/RX transceiver analog
VCC_HSSI_GXE E-Tile TX/RX transceiver analog
VCCH_GXE VCCH_GXE E-Tile TX/RX transceiver analog
VCCCLK_GXE VCCCLK_GXE E-Tile 2.5 V I/O supply
Table 7.   Agilex™ 7 P-Tile Power Rail Nets and Subsystem Details
PTC Rail Name Board Connections System Connections
VCC_HSSI_GXP VCCH 0.9 V P-Tile TX/RX transceiver digital
VCCFUSE_GXP P-Tile fuse
VCCRT_GXP P-Tile TX/RX transceiver analog
VCCH_GXP P1V8_GR2 P-Tile TX/RX analog
VCCCLK_GXP P-Tile 1.8 V I/O supply
Table 8.   Agilex™ 7 R-Tile Power Rail Nets and Subsystem Details
PTC Rail Name Board Connections System Connections
VCC_HSSI_GXR P0V9_GR1
  • R-Tile TX/RX transceiver digital
  • For AGI F-Tile and R-Tile ES device, VCC_HSSI_GXR is 0.95 V, hence requires a separate power rail
  • For AGI F-Tile and R-Tile production device, VCC_HSSI_GXR is 0.9 V, can be merged with VCCH
VCCED_GXR VCCED_GXR_0.9V_GR2/P0V9_GR1

R-Tile TX/RX transceiver digital.

Connect to an independent 0.9 V voltage regulator power supply in Group 2 for Agilex™ 7 F/I-series devices with F-Tile and R-Tile.

Connect to P0V9_GR1 in Group 1 for Agilex™ 7 M-series devices with F-Tile and R-Tile, and can be combined with VCC_HSSI_GXR.

VCCE_PLL_GXR VCCE_PLL_GXR R-Tile PLL reference signal power
VCCCLK_GXR P1V0_GR2 R-Tile DFE
VCCHFUSE_GXR R-Tile fuse sense
VCCRT_GXR VCCRT_GXR R-Tile TX/RX transceiver analog supply
VCCE_DTS_GXR VCCE_PLL_GXR —
VCCH_GXR P1V8_GR2/P1V8_GR3

R-Tile high voltage (1.8 V).

Connect to P1V8_GR2 via a filter for each Agilex™ 7 F/I-series devices with F-Tile and R-Tile.

Connect to P1V8_GR3 via a filter for each Agilex™ 7 M-Series devices with F-Tile and R-Tile.

Table 9.   Agilex™ 7 F-Tile Power Rail Nets and Subsystem Details
PTC Rail Name Board Connections System Connections
VCC_HSSI_GXF P0V8_GR1 F-Tile digital power supply, connect to P0V8_GR1 without filter
VCCERT_FGT_GXF P1V0_GR1 F-Tile general purpose analog supply
VCCERT1_FHT_GXF F-Tile high speed (HS) analog supply
VCCERT2_FHT_GXF F-Tile HS analog supply
VCCFUSECORE_GXF P1V0_GR2 F-Tile fuse supply
VCCFUSEWR_GXF F-Tile fuse sense WR
VCCEHT_FHT_GXF VCCEHT_FHT_GXF F-Tile HS high voltage supply
VCCH_FGT_GXF P1V8_GR2/P1V8_GR3

F-Tile general purpose high voltage supply.

Connect to P1V8_GR2 via a filter for each Agilex™ 7 F/I-series devices with F-Tile and R-Tile.

Connect to P1V8_GR3 via a filter for each Agilex™ 7 M-Series devices with F-Tile and R-Tile.

VCCCLK_GXF

F-Tile clock buffer supply.

Connect to P1V8_GR2 via a filter for each Agilex™ 7 F/I-series devices with F-Tile and R-Tile.

Connect to P1V8_GR3 via a filter for each Agilex™ 7 M-Series devices with F-Tile and R-Tile.

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