Agilex™ 7 Power Distribution Network Design Guidelines

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ID 683393
Date 10/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Agilex™ 7 Device Family PDN Design Summary 9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Agilex™ 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Agilex™ 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines

2.3.2. Power Rails Tolerance

This section describes the power rails tolerance and budget (AC tolerance + VR accuracy) on board at package level for the Agilex™ 7 device family. The rail tolerance must be met at the FPGA package ball. You must consider the following instructions to measure the rail tolerance:

  • VCCL (core power net) measurement is taken at the FPGA remote differential sense lines (there is assigned differential sense pins at FPGA package) with the scope set to bandwidth limited at 20 MHz.
  • VCCERT1_FHT_GXF has dedicated differential sense line at package level to compensate the IR drop at die level.
  • Other power rails (except for VCCL (core power)), the rail tolerance must be met at the board vias on the bottom layer directly connected to the package power balls.
  • For all other power rails with the objective to compensate the IR drop on those specific power rails, place their respective voltage regulator sense point within the FPGA pin field, connecting to one of the rail's BGA pins which represents the worst IR drop on the path.
Table 10.   Agilex™ 7 AGF Devices with only E-Tile and P-Tile PCB Power Rail Tolerance
Power Tree Rail Name Vnom (Required) (V) Recommended VR Accuracy (% of Vnom) Recommended VR Ripple (% of Vnom) Recommended AC Transient (% of Vnom) Maximum AC Tolerance + VR Accuracy (% of Vnom) 2
VCCL:
  • VCC/VCCP
  • VCCL_HPS
  • VCCPLLDIG_HPS
 VID (0.68, 0.8, 0.85) ±0.5% ±2.5% ±3%
P0V8_GR1:
  • VCCL_SDM
  • VCCPLLDIG_SDM
 0.8 ±0.5% ±2.5% ±3%
VCCH:
  • VCCH
  • VCCH_SDM
  • VCCFUSE_GXP
  • VCC_HSSI_GXP
  • VCC_HSSI_GXE
  • VCCRTPLL_GXE
  • VCCRT_GXE
  • VCCRT_GXP
 0.9 ±0.5% ±2.5% ±3%
P1V8_GR2 3:
  • VCCPT
  • VCCADC
  • VCCPLL_SDM
  • VCCPLL_HPS
 1.8 ±0.5% ±1% 4 ±3.5% ±5%
P1V8_GR23:
  • VCCCLK_GXP
  • VCCH_GXP
 1.8 ±0.5% ±0.5% ±2% ±3%
VCCH_GXE 1.1 ±0.5% ±0.5% ±2% ±3%
VCCCLK_GXE 2.5 ±0.5% ±0.5% ±3.5% ±5%
P1V2_GR3:
  • VCCIO_PIO
  • VCCIO_PIO_SDM
  • VCCRCORE
  • VCCA_PLL
 1.2 ±0.5% ±1%4 ±3.5% ±5%
P1V8_GR3:
  • VCCIO_SDM
  • VCCIO_HPS
  • VCCFUSE_SDM
 1.8 ±0.5% ±1%4 ±3.5% ±5%
Table 11.   Agilex™ 7 AGF and AGI Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance
Power Tree Rail Name Vnom (Required) (V) Recommended VR Accuracy (% of Vnom) Recommended VR Ripple (% of Vnom) Recommended AC Transient (% of Vnom) Maximum AC Tolerance + VR Accuracy (% of Vnom)2
VCCL:
  • VCC/VCCP
  • VCCL_HPS
  • VCCPLLDIG_HPS
 VID (0.68, 0.8, 0.85) ±0.5% ±2.5% ±3%
P0V8_GR1:
  • VCC_HSSI_GXF
  • VCCL_SDM
  • VCCPLLDIG_SDM
  • VCCH
  • VCCH_SDM
 0.8 ±0.5% ±2.5% ±3%
P0V9_GR1:
  • VCC_HSSI_GXR
  • VCCH_SDM
 0.9 ±0.5% ±2.5% ±3%
VCCE_PLL_GXR 1.0 ±0.5% ±2.0% ±2.5%
P1V0_GR13:
  • VCCERT_FGT_GXF
  • VCCERT1_FHT_GXF
  • VCCERT2_FHT_GXF
  • VCCRT_GXR
5 6 		1.0 ±0.5% ±2.0% ±2.5%
P1V0_GR23:
  • VCCFUSECORE_GXF/ VCCFUSEWR_GXF
  • VCCCLK_GXR
 1.0 ±0.5% ±2.5% ±3%
P1V0_GR23:
  • VCCHFUSE_GXR
 1.0 ±0.5% ±1%4 ±3.5% ±5%
VCCED_GXR 0.9 ±0.5% ±2.5% ±3%
VCCEHT_FHT_GXF 1.5 ±0.5% ±2.0% ±2.5%
P1V8_GR23:
  • VCCPT
  • VCCADC
  • VCCPLL_SDM
  • VCCPLL_HPS
 1.8 ±0.5% ±1%4 ±3.5% ±5%
P1V8_GR23:
  • VCCH_GXR
  • VCCH_FGT_GXF 7
1.8 ±0.5% ±2.0% ±2.5%
P1V8_GR23:
  • VCCCLK_GXF
 1.8 ±0.5% ±2.5% ±3%
P1V2_GR3:
  • VCCIO_PIO
  • VCCIO_PIO_SDM
  • VCCRCORE
  • VCCA_PLL
 1.2 ±0.5% ±1%4 ±3.5% ±5%
P1V8_GR3:
  • VCCIO_SDM
  • VCCIO_HPS
  • VCCFUSEWR_SDM
 1.8 ±0.5% ±1%4 ±3.5% ±5%
Table 12.   Agilex™ 7 AGM Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance
Power Tree Rail Name Vnom (Required) (V) Recommended VR Accuracy (% of Vnom) Recommended VR Ripple (% of Vnom) Recommended AC Transient (% of Vnom) Maximum AC Tolerance + VR Accuracy (% of Vnom)2
VCCL:
  • VCC/VCCP
  • VCCL_HPS
  • VCCPLLDIG_HPS
 VID (0.68, 0.8, 0.85) ±0.5% ±2.5% ±3%
P0V8_GR1:
  • VCC_HSSI_GXF
  • VCCL_SDM
  • VCCPLLDIG_SDM
  • VCCH
  • VCCH_SDM
  • VCCLPLL_NOC
  • VCCPLLDIG_NOC
 0.8 ±0.5% ±2.5% ±3%
P0V9_GR1:
  • VCC_HSSI_GXR
  • VCCH_SDM
  • VCCED_GXR
 0.9 ±0.5% ±2.5% ±3%
VCCE_PLL_GXR 1.0 ±0.5% ±2.0% ±2.5%
P1V0_GR13:
  • VCCERT_FGT_GXF
  • VCCERT1_FHT_GXF
  • VCCERT2_FHT_GXF
  • VCCRT_GXR
5 6 		1.0 ±0.5% ±2.0% ±2.5%
P1V0_GR13:
  • VCCFUSECORE_GXF 7/ VCCFUSEWR_GXF
  • VCCCLK_GXR
 1.0 ±0.5% ±2.5% ±3%
P1V0_GR13:
  • VCCHFUSE_GXR
 1.0 ±0.5% ±1%4 ±3.5% ±5%
VCCEHT_FHT_GXF 1.5 ±0.5% ±2.0% ±2.5%
P1V8_GR3a3:
  • VCCPT
  • VCCADC
  • VCCPLL_SDM
  • VCCPLL_HPS
  • VCCIO_SDM
  • VCCIO_HPS
  • VCCFUSEWR_SDM
 1.8 ±0.5% ±1%4 ±3.5% ±5%
P1V8_GR3a3:
  • VCCH_GXR
  • VCCH_FGT_GXF7
1.8 ±0.5% ±2.0% ±2.5%
P1V8_GR3a3:
  • VCCCLK_GXF
 1.8 ±0.5% ±2.5% ±3%
P1V8_GR3a3:
  • VCCPLL_NOC
  • VCCIO_NOC
 1.8 ±0.5% ±0.5% ±2.0% ±3%
VCCM_PUMP_HBM 2.5 ±0.5% ±1%4 ±3.5% ±5%
P1V2_GR3b:
  • VCCIO_PIO
  • VCCIO_PIO_SDM
  • VCCRCORE
  • VCCIO_UIB
 1.2 ±0.5% ±1%4 ±3.5% ±5%

The actual specification for each power rail at package level is listed in the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series . To reduce the PCB cost, some power rails are merged by using only a single voltage regulator to feed the power rails. The AC + DC specification in this design guideline is based on this design. However, you have the option to not combine the power rails on the PCB in your design.

You can combine the analog power rails on the PCB (provided that the nominal voltages are the same) by using a single voltage regulator on the PCB to feed the power rails to achieve the minimum cost. If you implement this design, you must ensure the power rail specifications of the combined power rails on the PCB and voltage regulator must follow the most stringent specification of those package power rails.

The analog power rails can also be merged with the digital power rails if they are the same voltage and are in the same power-up or power-down sequence. However, ensure using the noise isolation filter from the digital power rails to analog power rails (since they are more sensitive to noise).

The Agilex™ 7 AGF Devices with only E-Tile and P-Tile PCB Power Rail Tolerance , Agilex™ 7 AGF and AGI Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance , and Agilex™ 7 AGM Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance tables shows the power rail tolerance (AC tolerance + VR accuracy) based on the power tree in the Recommended Agilex™ 7 AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices figure.
If a different power tree in the Recommended Agilex™ 7 AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices figure is used, the rail tolerance of each power net must fall into their recommended grouping category in the Agilex™ 7 AGF Devices with only E-Tile and P-Tile PCB Power Rail Tolerance , Agilex™ 7 AGF and AGI Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance , and Agilex™ 7 AGM Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance tables.
2 The specification stands for VR accuracy + (VR ripple + AC transient) rail tolerance and must be measured and met at package pin/ball.
3 These power rails have different tolerances, when merged in one VR, use the tight tolerance requirement in board design.
4 If you select a voltage regulator with lower than 1% voltage regulator ripple specification, the extra margin is added to the recommended AC transient specification.
5 The P1V0_GR1 specification for these individual specific power rails are ±2.5% (AC tolerance + VR accuracy) at package pin.This specification is also up to 1 MHz. The voltage regulator ripple specification is 5 mV p-p maximum. The AC noise specification above 1 MHz at package pin is ±15 mV (30 mV p-p). This can be measured by a high pass filter probe above 1 MHz.
6 The VCCERT_FGT_GXF, VCCERT1_FHT_GXF, VCCERT2_FHT_GXF, and VCCRT_GXR can be merged to P1V0_GR1. The final specification of the merged power rail is the most stringent among those power rails.
7 The VCCH_FGT_GXF specification for this individual power rail per Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series is ±2.5% (VR accuracy + AC tolerance). This applies up to 1 MHz (use of probe with low pass filter at 1 MHz at package pin, the voltage regulator ripple specification is 5 mV p-p maximum). The AC noise specification above 1 MHz at package pin is ±15 mV (30 mV p-p). This can be measured by a high pass filter probe above 1 MHz.
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