Agilex™ 7 Power Distribution Network Design Guidelines

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ID 683393
Date 10/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused Tiles 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Agilex™ 7 Device Family PDN Design Summary 9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Agilex™ 7 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages 2.1.2.2. Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages 2.1.2.3. Recommended Power Tree for the Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Agilex™ 7 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile Agilex™ 7 E-Tile Board-Level Decoupling Capacitors Summary 2.4.3. Agilex™ 7 P-Tile Board-Level Decoupling Capacitors Summary 2.4.4. Agilex™ 7 F-Tile Board-Level Decoupling Capacitors Summary 2.4.5. Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors and Power Flooding Guides 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. P-Tile Rail LC Filter Board Scheme and Connection 4.2. E-Tile Rail LC Filter Board Scheme and Connection 4.3. F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator 4.4. R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused Tiles x
5.1. PDN Design Guideline for Unused E-Tile 5.2. PDN Design Guideline for Unused P-Tile 5.3. PDN Design Guideline for Unused R-Tile 5.4. PDN Design Guideline for Unused F-Tile
1. Agilex™ 7 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused Tiles
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 7 Device Family PDN Design Summary
9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines

9. Document Revision History for the Agilex™ 7 Power Distribution Network Design Guidelines

Document Version Changes
2024.10.18
  • Updated Table: Agilex™ 7 F-Tile Power Rail Nets and Subsystem Details:
    • Corrected rail name VCCLK_GXF to VCCCLK_GXF.
    • Updated system connection description for VCCCLK_GXF.
  • Made minor editorial edits to the document.
2024.08.09 Updated the following figures:
  • Figure: Recommended Agilex™ 7 AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices
  • Figure: Recommended Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon
  • Figure: Recommended Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Engineering Sample (ES) Silicon.
2024.07.08
  • Renamed the document title to Agilex™ 7 Power Distribution Network Design Guidelines.
  • Updated Table: Device Guidelines Status for Agilex™ 7 Devices (F-Series):
    • Added AGF 006/008/012/014 (R24D).
    • Updated the guideline status for the following devices from Advanced to Preliminary:
      • AGF 006/008 (R16A)
      • AGF 006/008/012/014/019/022/023/027 (R24C)
      • AGF 019/022/023/027 (R31C)
  • Updated Table: Device Guidelines Status for Agilex™ 7 Devices (I-Series):
    • Added AGI 041 (R31E).
    • Updated the guideline status for the following devices from Advanced to Preliminary:
      • AGI 022/027 (R31A)
      • AGI 041 (R29D)
      • AGI 041 (R31B)
  • Updated Table: Device Guidelines Status for Agilex™ 7 Devices (M-Series):
    • Added AGM 039 (R47B).
    • Corrected device name for R31B package to AGM 039 only.
  • Removed Table: Agilex™ 7 Device PCB Power Rail Tolerance.
  • Added the following tables:
    • Table: Agilex™ 7 AGF Devices with only E-Tile and P-Tile PCB Power Rail Tolerance
    • Table: Agilex™ 7 AGF and AGI Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance
    • Table: Agilex™ 7 AGM Devices with only F-Tile, or both F-Tile and R-Tile PCB Power Rail Tolerance
    • Table: Agilex™ 7 F-Series, I-Series, and M-Series Decoupling Capacitors Summary
    • Table: Agilex™ 7 Device Family Transient and Step Load Specifications at Package Pin
  • Updated the following figures:
    • Figure: Recommended Agilex™ 7 AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices
    • Figure: Recommended Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon
    • Figure: Recommended Agilex™ 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Engineering Sample (ES) Silicon.
  • Updated the system connections for VCCH_GXP and VCCCLK_GXP in Table: Agilex™ 7 P-Tile Power Rail Nets and Subsystem Details.
  • Updated Load Line Requirements.
  • Made editorial edits throughout the document.
2023.12.04
  • Added the R31B package support in Table: Device Guidelines Status for Agilex™ 7 Devices (M-Series).
  • Updated the AGM039/AGM032 device package support in Table: Agilex™ 7 Device Family Transient and Step Load Specifications at Package Pin.
  • Updated the AGM039/AGM032 device package support in Table: Agilex™ 7 FPGA F-Series, I-Series, and M-Series Decoupling Capacitors Summary.
2023.09.29
  • Updated the Power Nets and Transient Specifications section.
  • Updated the Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary section.
  • Updated the Agilex™ 7 R-Tile Board-Level Decoupling Capacitors Summary section.
  • Updated the Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails section.
  • Updated Table: Device Guidelines Status for Agilex™ 7 Devices (F-Series).
  • Updated Table: Device Guidelines Status for Agilex™ 7 Devices (I-Series).
  • Updated Table: Agilex™ 7 R-Tile Power Rail Nets and Subsystem Details.
  • Updated Table: Agilex™ 7 F-Tile Power Rail Nets and Subsystem Details.
  • Updated Table: Agilex™ 7 Device Family Transient and Step Load Specifications at Package Pin.
  • Updated Table: Agilex™ 7 FPGA F-Series, I-Series, and M-Series Decoupling Capacitors Summary.
  • Updated Table: Recommended Capacitors Used for the LC Filter.
  • Updated Figure: Recommended Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon.
  • Updated the figure title in Figure: Connection Requirement and Filter Recommendation for VCCH_GXR per Tile.
2023.06.26
  • Added reference to AN 974: Stratix® 10 and Agilex™ 7 SmartVID Debug Checklist and Voltage Regulator Guidelines.
  • Updated the Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary section to include AGI041 device.
  • Updated Table: Device Guidelines Status for Agilex™ 7 Devices (I-Series) to include AGI 041 R29D and R31B packages.
  • Updated Table: Agilex™ 7 Device Family Transient and Step Load Specifications at Package Pin to include AGI041 device.
  • Updated Table: Agilex™ 7 FPGA F-Series, I-Series, and M-Series Decoupling Capacitors Summary to include AGI041 R29D and R31B packages.
2023.04.03
  • Added support for the Intel Agilex® 7 M-Series devices.
  • Added Recommended Power Tree for the Intel Agilex® 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Device Packages section.
  • Added P1V2_GR3 Filters Recommendation for Device Fabric section.
  • Added P0V8_GR1 Filters Recommendation for Device Fabric section.
  • Added VCCL Filters Recommendation for Device Fabric section.
  • Added Table: Device Guidelines Status for Intel Agilex® 7 Devices (M-Series).
  • Added Table: Intel Agilex® 7 AGM (with only F-Tile, R-Tile, or Both) FPGA Package Power Rail Nets and Subsystem Details.
  • Added Figure: Recommended Intel Agilex® 7 AGM (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Engineering Sample (ES) Silicon.
  • Added Figure: Example of Board Power Flooding.
  • Added Figure: VCCPLL_NOC LC Filter Recommendation.
  • Added Figure: VCCLPLL_NOC LC Filter Recommendation.
  • Added Figure: VCCPLLDIG_NOC LC Filter Recommendation.
  • Updated the Power Tree section.
  • Updated the Recommended Power Tree for the Agilex™ 7 Devices with only P-Tile and E-Tile in the Device Packages section.
  • Updated the Recommended Power Tree for the Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Device Packages.
  • Updated the Rail Merger Requirements section.
  • Updated the Power Nets section.
  • Updated the Agilex™ 7 Package Power Nets and Subsystems Details section.
  • Updated the Power Rails Tolerance section.
  • Updated the Intel Agilex® 7 FPGA Packages Board-Level Decoupling Capacitors Summary section.
  • Updated the P1V8_GR2 ( Intel Agilex® 7 F-Series and I-Series)/P1V8_GR3 ( Intel Agilex® 7 M-Series) Filters Recommendation for Device Fabric section.
  • Updated the Agilex™ 7 FPGA Packages Board-Level Decoupling Capacitors Summary section.
  • Updated the Board Decoupling Capacitors and Power Flooding Guides section.
  • Updated the Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails section.
  • Updated Table: Intel Agilex® 7 Device Family Transient and Step Load Specifications at Package Pin.
  • Updated Table: Device Guidelines Status for Agilex™ 7 Devices (I-Series).
  • Updated Table: Agilex™ 7 AGF (with only E-Tile and P-Tile), Agilex™ 7 AGF (with only F-Tile), and Agilex™ 7 AGI (with only F-Tile, R-Tile, or both) FPGA Package Power Rail Nets and Subsystem Details.
  • Updated Table: Intel Agilex® 7 R-Tile Power Rail Nets and Subsystem Details.
  • Updated Table: Intel Agilex® 7 F-Tile Power Rail Nets and Subsystem Details.
  • Updated Table: Intel Agilex® 7 Device PCB Power Rail Tolerance.
  • Updated Table: Intel Agilex® 7 FPGA F-Series, I-Series, and M-Series Decoupling Capacitors Summary.
  • Updated Table: Agilex™ 7 E-Tile Decoupling Capacitors Summary per Tile.
  • Updated Table: Agilex™ 7 Device Family Transient and Step Load Specifications at Package Pin.
  • Updated Table: Recommended Inductors and Ferrite Beads for the LC Filter.
  • Updated notes (1) and (3) in Figure: Recommended Agilex™ 7 AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon.
  • Updated Figure: VCCADC, VCCPLL_SDM, and VCCPLL_HPS Filter Recommendation.
  • Updated Figure: VCCA_PLL Filter Recommendation.
  • Updated Figure: VCCPLLDIG_SDM Filter Recommendation.
  • Updated Figure: VCCPLLDIG_HPS Filter Recommendation.
  • Updated Figure: Filter Recommendation for VCCCLK_GXP per Tile.
  • Updated Figure: Filter Recommendation for VCCH_GXP per Tile.
  • Updated Figure: Filter Recommendation for VCCRT_GXP per Tile.
  • Updated Figure: Filter Recommendation for VCCRT_GXP per Tile (Low Power Scenario).
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCRT_GXE per Tile.
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCRT_GXE per Tile (Low Power Scenario).
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCRTPLL_GXE per Tile.
  • Updated Figure: Filter Recommendation for VCCH_FGT_GXF per Tile.
  • Updated Figure: Filter Recommendation for VCCCLK_GXF per Tile.
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCH_GXR.
  • Updated the product family name to " Intel Agilex® 7".
  • Retitled the document from AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines to AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines.
  • Removed Table: Required Rail Connections.
  • Removed Figure: Recommended Intel Agilex® 7 AGF014 (with only E-Tile and P-Tile) Power Tree for Engineering Sample (ES) Silicon.
  • Removed Figure: VCCPT LC Filter Recommendation.
  • Removed Figure: VCCPT LC Filter Recommendation (Low Power Scenario).
  • Removed Figure: Filter Recommendation for VCCERT1_FHT_GXF per Tile.
  • Removed Figure: Filter Recommendation for VCCERT2_FHT_GXF per Tile.
  • Removed Figure: Filter Recommendation for VCCEHT_FHT_GXF per Tile.
2022.11.30
  • Added the Device Guidelines Status for Intel® Agilex™ Devices section.
  • Added Figure: VCCPT LC Filter Recommendation (Low Power Scenario).
  • Added Figure: VCCA_PLL LC Filter Recommendation (Low Power Scenario).
  • Added Figure: Filter Recommendation for VCCH_GXP per Tile (Low Power Scenario).
  • Added Figure: Filter Recommendation for VCCRT_GXP per Tile (Low Power Scenario).
  • Added Figure: Connection Requirement and Filter Recommendation for VCCRT_GXE per Tile (Low Power Scenario).
  • Updated the Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails section.
  • Updated the Power Rails Tolerance section.
  • Updated the Intel® Agilex™ FPGA Packages Board-Level Decoupling Capacitors Summary section.
  • Updated the Board Decoupling Capacitors Guide section.
  • Updated the FPGA Core Fabric VCC Voltage Regulator Selection section.
  • Updated the Remote Sense Connections section.
  • Updated Table: Required Rail Connections.
  • Updated Table: Intel® Agilex™ AGF (with only E-Tile and P-Tile), Intel® Agilex™ AGF (with only F-Tile), and Intel® Agilex™ AGI (with only F-Tile, R-Tile, or both) FPGA Package Power Rail Nets and Subsystem Details.
  • Updated Table: Intel® Agilex™ R-Tile Power Rail Nets and Subsystem Details.
  • Updated Table: Intel® Agilex™ Device PCB Power Rail Tolerance.
  • Updated Table: Intel® Agilex™ Device Family Transient and Step Load Specifications at Package Pin.
  • Updated Table: Intel® Agilex™ F-Series and I-Series FPGA Decoupling Capacitors Summary.
  • Updated Table: Intel® Agilex™ E-Tile Decoupling Capacitors Summary per Tile.
  • Updated Table: Intel® Agilex™ P-Tile Decoupling Capacitors Summary per Tile.
  • Updated Table: List of Supported Controllers and Power Stages.
  • Updated note (1) in Figure: Recommended Intel® Agilex™ AGF014 (with only E-Tile and P-Tile) Power Tree for Engineering Sample (ES) Silicon.
  • Updated note (1) in Figure: Recommended Intel® Agilex™ AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices.
  • Updated note (2) in Figure: Recommended Intel® Agilex™ AGI or AGF (with only F-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon.
  • Updated Figure: Filter Recommendation for VCCRT_GXP per Tile.
  • Updated Figure: Filter Recommendation for VCCH_GXP per Tile.
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCRTPLL_GXE per Tile.
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCH_GXR.
2022.11.30 Updated Figure: Recommended Intel® Agilex™ AGI or AGF (with only F-Tile, R-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon.
2022.09.22
  • Added the VCCBAT RC Circuit Using the Device Security AES BBRAM Key section.
  • Added Figure: VCCBAT Rail RC Circuit Recommendation.
  • Updated note (6) in Figure: Recommended Intel® Agilex™ AGF014 (with only E-Tile and P-Tile) Power Tree for Engineering Sample (ES) Silicon.
  • Updated note (6) in Figure: Recommended Intel® Agilex™ AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices.
  • Updated note (9) in Figure: Recommended Intel® Agilex™ AGI or AGF (with only F-Tile, R-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon.
2022.09.06
  • Updated Figure: Recommended Intel® Agilex™ AGF014 (with only E-Tile and P-Tile) Power Tree for Engineering Sample (ES) Silicon.
  • Updated Figure: Recommended Intel® Agilex™ AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices.
  • Updated Figure: Recommended Intel® Agilex™ AGI or AGF (with only F-Tile, R-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon.
  • Updated the VCCRCORE system connections description in Table: Intel® Agilex™ AGF (with only E-Tile and P-Tile), Intel® Agilex™ AGF (with only F-Tile), and Intel® Agilex™ AGI (with only F-Tile, R-Tile, or both) FPGA Package Power Rail Nets and Subsystem Details.
2022.06.02
  • Added Figure: VCCPLLDIG_SDM Filter Recommendation.
  • Added Figure: VCCPLLDIG_HPS Filter Recommendation.
  • Updated the Power Budget section.
  • Updated the Rail Merger Requirements section.
  • Updated the Intel® Agilex™ R-Tile Board-Level Decoupling Capacitors Summary section.
  • Updated the FPGA Core Fabric VCC Voltage Regulator Selection section.
  • Updated the P-Tile Rail LC Filter Board Scheme and Connection section.
  • Updated the E-Tile Rail LC Filter Board Scheme and Connection section.
  • Updated the F-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator section.
  • Updated the R-Tile Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator section.
  • Updated the PCB Voltage Regulator Recommendation for PCB Power Rails section.
  • Updated the VCCA_PLL: Difference between Intel® Agilex™ AGF014 2486A ES and Production Silicons section.
  • Updated the Intel® Agilex™ AGF014/AGF012/AGF008/AGF006, Intel® Agilex™ AGI027/AGI023/AGI022/AGI019, and Intel® Agilex™ AGF027/AGF023/AGF022/AGF019 FPGA Packages Board-Level Decoupling Capacitors Summary section.
  • Updated Table: Required Rail Connections.
  • Updated Table: Intel® Agilex™ AGF (with only E-Tile and P-Tile), Intel® Agilex™ AGF (with only F-Tile), and Intel® Agilex™ AGI (with only F-Tile, R-Tile, or both) FPGA Package Power Rail Nets and Subsystem Details.
  • Updated Table: Intel® Agilex™ Device PCB Power Rail Tolerance.
  • Updated Table: Intel® Agilex™ Device Family Transient and Step Load Specifications at Package Pin.
  • Updated Table: Intel® Agilex™ AGF012/AGF014, Intel® Agilex™ AGI027/AGI023/AGI022, and Intel® Agilex™ AGF027/AGF023/AGF022 FPGA Decoupling Capacitors Summary.
  • Updated Table: Intel® Agilex™ E-Tile Decoupling Capacitors Summary per Tile.
  • Updated Table: Intel® Agilex™ P-Tile Decoupling Capacitors Summary per Tile.
  • Updated Table: List of Supported Controllers and Power Stages.
  • Updated Figure: Recommended Intel® Agilex™ AGF014 (with only E-Tile and P-Tile) Power Tree for Engineering Sample (ES) Silicon.
  • Updated Figure: Recommended Intel® Agilex™ AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices.
  • Updated Figure: Recommended Intel® Agilex™ AGI or AGF (with only F-Tile, R-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon.
  • Updated Figure: VCC/VCCP Core Voltage Regulator Design Implemented on the Intel® Agilex™ AGF014 2486A FPGA Development Kits.
  • Updated Figure: VCCADC, VCCPLL_SDM, and VCCPLL_HPS Filter Recommendation.
  • Updated Figure: VCCPT LC Filter Recommendation.
  • Updated Figure: VCCA_PLL Filter Recommendation.
  • Updated Figure: Filter Recommendation for VCCCLK_GXP per Tile.
  • Updated Figure: Filter Recommendation for VCCH_GXP per Tile.
  • Updated Figure: Filter Recommendation for VCCRT_GXP per Tile.
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCRT_GXE per Tile.
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCRTPLL_GXE per Tile.
  • Updated Figure: Filter Recommendation for VCCH_FGT_GXF per Tile.
  • Updated Figure: Filter Recommendation for VCCERT_FGT_GXF per Tile.
  • Updated Figure: Filter Recommendation for VCCERT1_FHT_GXF per Tile.
  • Updated Figure: Filter Recommendation for VCCERT2_FHT_GXF per Tile.
  • Updated Figure: Filter Recommendation for VCCEHT_FHT_GXF per Tile.
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCH_GXR.
2022.04.15
  • Updated Figure: Recommended Intel® Agilex™ AGF014 (with only E-Tile and P-Tile) Power Tree for Engineering Sample (ES) Silicon.
  • Updated Figure: Recommended Intel® Agilex™ .
  • Updated Figure: Recommended Intel® Agilex™ AGI or AGF (with only F-Tile, R-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon.
  • Updated the VCCBAT board connections and system connections in Table: Intel® Agilex™ AGF (with only E-Tile and P-Tile), Intel® Agilex™ AGF (with only F-Tile), and Intel® Agilex™ AGI (with only F-Tile, R-Tile, or both) FPGA Package Power Rail Nets and Subsystem Details.
  • Updated Table: Intel® Agilex™ AGF012/AGF014, Intel® Agilex™ AGI027/AGI023/AGI022, and Intel® Agilex™ AGF027/AGF023/AGF022 FPGA Decoupling Capacitors Summary.
2022.03.08
  • Updated the OTN protocol standards for E-tile in the Intel® Agilex™ E-Tile Board-Level Decoupling Capacitors Summary section.
  • Updated the VCCRCORE pin name.
2021.10.18
  • Updated Figure: Recommended Intel® Agilex™ AGF014 (with only E-Tile and P-Tile) Power Tree for Engineering Sample (ES) Silicon.
  • Updated Figure: Recommended Intel® Agilex™ AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices.
  • Updated Figure: Recommended Intel® Agilex™ AGI or AGF (with only F-Tile, R-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon.
  • Updated Figure: VCC/VCCP Core Voltage Regulator Design Implemented on the Intel® Agilex™ AGF014 2486A FPGA Development Kits to remove typo.
  • Updated the VCCFUSEWR_SDM voltage in Table: Intel® Agilex™ Device PCB Power Rail Tolerance.
  • Removed the Power Sequencing Guidelines chapter and added reference to the Intel® Agilex™ Power Management User Guide for the PUS/PDS requirements.
2021.07.23
  • Added the PCB PDN Design Guideline for Unused Tiles section.
  • Added Figure: VCCPT LC Filter Recommendation.
  • Updated the Power Tree section.
  • Updated the Power Tree Updates for Intel® Agilex™ AGF014 2486A Production Silicon section.
  • Updated the Power Nets and Transient Specifications section.
  • Updated the Intel® Agilex™ AGF012/AGF014, Intel® Agilex™ AGI027/AGI023/AGI022, and Intel® Agilex™ AGF027/AGF023/AGF022 FPGA Packages Board-Level Decoupling Capacitors Summary section.
  • Updated the Board Decoupling Capacitors Guide section.
  • Updated the FPGA Core Fabric VCC Voltage Regulator Selection section.
  • Updated the Remote Sense Connections section.
  • Updated the VCC Core Board Current Slew Rate section.
  • Updated the Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails section.
  • Updated the P-Tile Rail LC Filter Board Scheme and Connection section.
  • Updated the PCB Voltage Regulator Recommendation for Other Power Rails section.
  • Updated the Board Power Delivery Network Simulations section.
  • Updated the Intel® Agilex™ Device Family PDN Design Summary section.
  • Updated Table: Intel® Agilex™ Device Power Rail Grouping for the PUS Purpose.
  • Updated Table: Required Rail Connections.
  • Updated Table: Intel® Agilex™ AGF (with only E-Tile and P-Tile), Intel® Agilex™ AGF (with only F-Tile), and Intel® Agilex™ AGF Devices (with only E-Tile and P-Tile) Power Tree for AGI (with only F-Tile, R-Tile, or both tiles) FPGA Package Power Rail Nets and Subsystem Details.
  • Updated Table: Intel® Agilex™ E-Tile Power Rail Nets and Subsystem Details.
  • Updated Table: Intel® Agilex™ P-Tile Power Rail Nets and Subsystem Details.
  • Updated Table: Intel® Agilex™ R-Tile Power Rail Nets and Subsystem Details.
  • Updated Table: Intel® Agilex™ F-Tile Power Rail Nets and Subsystem Details.
  • Updated Table: Intel® Agilex™ Device PCB Power Rail Tolerance.
  • Updated Table: Intel® Agilex™ Device Family Transient and Step Load Specifications at Package Pin.
  • Updated Table: Intel® Agilex™ AGF012/AGF014, Intel® Agilex™ AGI027/AGI023/AGI022, and Intel® Agilex™ AGF027/AGF023/AGF022 Decoupling Capacitors Summary.
  • Updated Table: Intel® Agilex™ E-Tile Decoupling Capacitors Summary per Tile.
  • Updated Table: Intel® Agilex™ P-Tile Decoupling Capacitors Summary per Tile.
  • Updated Table: Intel® Agilex™ F-Tile Decoupling Capacitors Summary per Tile.
  • Updated Table: Intel® Agilex™ R-Tile Decoupling Capacitors Summary per Tile.
  • Updated Figure: Recommended Intel® Agilex™ AGF014 (with only E-Tile and P-Tile) Power Tree for Engineering Sample (ES) Silicon.
  • Updated Figure: Recommended Intel® Agilex™ AGF Devices (with only E-Tile and P-Tile) Power Tree for Production Devices.
  • Updated Figure: Recommended Intel® Agilex™ AGI or AGF (with only F-Tile, R-Tile, or both F-Tile and R-Tile) Power Tree for Production Silicon.
  • Updated Figure: Filter Recommendation for VCCH_GXP.
  • Updated Figure: Filter Recommendation for VCCRT_GXP.
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCRT_GXE.
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCRTPLL_GXE.
  • Updated Figure: Filter Recommendation for VCCH_FGT_GXF.
  • Updated Figure: Connection Requirement and Filter Recommendation for VCCH_GXR.
  • Updated Figure: Time Domain PDN Test Bench Example for Intel® Agilex™ AGF014 VCC Core.
  • Edited all "caps" and "decaps" to "capacitors" and "decoupling capacitors".
2021.06.02
  • Added VCCH_GXP and VCCCLK_GXP rails to Group 9 Rail 2 column in Table: Required Rail Connections.
  • Updated VCCBAT_SDM power rail name to VCCBAT.
  • Updated Figure: Filter Recommendation for VCCRT_GXP.
  • Removed VCCBAT from Table: Intel® Agilex™ Device Power Rail Grouping for the PUS Purpose.
  • Removed F-series and I-series references.
2021.03.12
  • Added the F-tile and R-tile power rails in the following tables:
    • Table: Required Rail Connections
    • Table: Intel® Agilex™ F-Series 2486A and 2581A FPGA Package Power Rail Nets and Subsystem Details
    • Table: Intel® Agilex™ Device Rail Tolerance
    • Table: Intel® Agilex™ Device Family Transient and Step Load Specifications at Package Pin
    • Table: Intel® Agilex™ F-Series 2486A and 2581A FPGA Decoupling Capacitors Summary
  • Added Table: Intel® Agilex™ F-Tile Decoupling Capacitors Summary.
  • Added Table: Intel® Agilex™ R-Tile Decoupling Capacitors Summary.
  • Added Table: Intel® Agilex™ R-Tile Power Rail Nets and Subsystem Details.
  • Added Table: Intel® Agilex™ F-Tile Power Rail Nets and Subsystem Details.
  • Added the Recommended Power Tree for the Intel® Agilex™ I-Series (2957A: R-Tile and F-Tile) Device Packages section.
  • Added the P1V8_GR2 Filters Recommendation for Device Fabric section.
  • Added the F-Tile Rail LC Filter Board Scheme and Connection section.
  • Added the R-Tile Rail LC Filter Board Scheme and Connection section.
  • Added Figure: VCCADC, VCCPLL_SDM, and VCCPLL_HPS Filter Recommendation.
  • Added Figure: VCCA_PLL Filter Recommendation.
  • Updated Table: Intel® Agilex™ Device Power Rail Grouping for the PUS Purpose.
  • Updated Figure:VCC/VCCP Core Voltage Regulator Design Implemented on the Intel® Agilex™ AGF014 2486A FPGA Development Kits.
  • Updated Figure: Filter Recommendation for VCCRT_GXP.
  • Updated the Power-Down Sequencing (PDS) section.
  • Updated the Power Budget section.
  • Updated the Power Rails Tolerance section.
  • Updated the Decoupling Capacitors Recommendation section.
  • Updated the Board Decoupling Capacitors Guide section.
  • Updated the Remote Sense Connections section.
  • Updated the section title FPGA Core Fabric VCCL Voltage Regulator Selection to FPGA Core Fabric VCC Voltage Regulator Selection.
2020.12.18 Updated Figure: Recommended F-Series 2486A and 2581A Power Tree for Production Silicon to correct VCCCLX_GXP to VCCCLK_GXP.
2020.12.16 Updated Figure: Recommended F-Series 2486A and 2581A Power Tree for Production Silicon to correct the power group for VCCA_PLL from 2 to 3.
2020.12.05
  • Updated references to "ES silicon" to "early silicon" throughout the document.
  • Updated Figure: Recommended F-Series 2486A Power Tree for Early Silicon.
  • Updated Figure: Recommended F-Series 2486A and 2581A Power Tree for Production Silicon.
  • Updated the Board Decoupling Capacitors Guide topic:
    • Updated the VCCH cavity decapacitors on bottom side from 6x 0603 22µ to 4x 0603 22µ.
    • Added a note to clarify that the power tree and number of decoupling capacitors within cavity on Intel® Agilex™ development kit boards may be slightly different than what has been recommended due to early release of silicon and guideline.
  • Updated Table: Intel® Agilex™ F-Series 2486A and 2581A FPGA Decoupling Capacitors Summary.
  • Updated Table: Required Rail Connections.
2020.08.25
  • Updated Figure: Recommended F-Series 2486A Power Tree for ES Silicon.
  • Updated note (1) in Figure: Recommended F-Series 2486A and 2581A Power Tree for Production Silicon.
2020.08.19 Initial release.
Level Two Title