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Visible to Intel only — GUID: uqt1538487949400
Ixiasoft
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide
You can use the Example Designs tab and the Generate Example Designs button in the IP Parameter Editor Pro window to specify and generate synthesis and simulation example design file sets with which you can validate your HBM2 IP.
The generated design example reflects the parameterization that you set in the IP Parameter Editor Pro window. You can generate a design example to specifically match an Intel FPGA development kit for your evaluation. Or you can generate a design example to match your own actual system requirements, as a starting point for creating your own system.
- Creating an Intel Quartus Prime Project for Your HBM2 System
- Configuring the High Bandwidth Memory (HBM2) Interface Intel FPGA IP
- IP Parameter Editor Pro Guidelines for High Bandwidth Memory (HBM2) Interface Intel FPGA IP
- Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example
- Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency
- Generating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example for Simulation
- Regenerating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example After Modification