2.3. IP Parameter Editor Pro Guidelines for High Bandwidth Memory (HBM2) Interface Intel FPGA IP
Parameter Editor Tab | Guideline |
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General | Correctly enter the following parameters to reflect your Intel FPGA development kit requirement or your HBM2 interface and system requirement:
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Controller # | Set the parameters to reflect your actual HBM2 interface and system requirement for the controller. |
Diagnostic | For initial project investigations, you may use the default settings on the Diagnostic tab. For hardware testing using the synthesizable design example, check the Enable In-System-Sources-and-Probes checkbox to allow you to easily control and monitor the High Bandwidth Memory (HBM2) Interface Intel FPGA IP example design system through the Intel® Quartus® Prime software. For efficiency testing on both synthesis and simulation designs, check the Use Efficiency Pattern and Enable Efficiency Test Mode checkboxes. Keep both the read count and write count the same to ensure that the validity check passes. Select the Data Sequence (Random/Sequential) option for testing, and check Enable data check for efficiency measurement for data validity check. For simulation, if you want the simulation to report the efficiency number for each HBM channel that you have enabled, check the Enable Efficiency Monitor checkbox. (For hardware testing using the synthesizable example design project, you should not enable the Efficiency Monitor, as this feature reduces the frequency at which the interface will close timing in the core clock domain.) You can also use the other parameters on the Diagnostics tab to assist you in evaluating, verifying and debugging the High Bandwidth Memory (HBM2) Interface Intel FPGA IP. |
Example Designs | To get the correct design example file sets, ensure that you check either the Simulation or Synthesis checkbox, or both, in the Example Design Files section. The generated design example is a complete HBM2 system consisting of the High Bandwidth Memory (HBM2) Interface Intel FPGA IP and a driver that generates random traffic to validate the memory interface. |