High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

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ID 683379
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description 4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
1.1. Release Information
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2 System 2.2. Configuring the High Bandwidth Memory (HBM2) Interface Intel FPGA IP 2.3. IP Parameter Editor Pro Guidelines for High Bandwidth Memory (HBM2) Interface Intel FPGA IP 2.4. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example 2.5. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency 2.6. Generating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example for Simulation 2.7. Regenerating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example After Modification
3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description x
3.1. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Synthesis Design Example 3.2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Simulation Design Example 3.3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Interface tab
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description
4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

3.2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Simulation Design Example

The simulation design example contains the following major blocks.
  • The simulation example includes all the major blocks that exist in the synthesis design example, including a traffic generator pair, and an instance of the High Bandwidth Memory (HBM2) Interface Intel FPGA IP and external core clock I/O PLL. These blocks default to abstract simulation models where appropriate for rapid simulation. The design example may also include an Efficiency Monitor block for every HBM channel that you have enabled. The Efficiency Monitor block reports the efficiency number for the particular HBM channel at the end of simulation.
  • An HBM2 memory model, which acts as a generic model that conforms to the HBM2 protocol specifications. Frequently, HBM2 vendors provide simulation models for their specific HBM2 components that you can download from their websites.
  • A simulation checker, which monitors the status signals from the HBM2 IP and the traffic generator, to signal an overall pass or fail condition.
  • The clock source and reset source instances which are the Bus Functional Model (BFM) that generates the reference clock and reset signal.
Figure 5.  Simulation Design Example with Efficiency Monitor Enabled
Note: Unlike other styles of memory interface where the testbench normally wraps the synthesis example design top-level file, for the High Bandwidth Memory (HBM2) Interface Intel FPGA IP, the Traffic Generator and other non-High Bandwidth Memory (HBM2) Interface Intel FPGA IP components are instantiated in the top-level testbench file.
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