3.1. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Synthesis Design Example
The synthesis design example contains the following major blocks.
- An instance of the High Bandwidth Memory (HBM2) Interface Intel FPGA IP that manages the read, write, and other operations to the HBM2 device.
- Two independent traffic generators for every HBM channel enabled (one traffic generator for each HBM Pseudo-channel). The traffic generator is a synthesizable AXI-4 type example driver that implements a pseudo-random pattern of reads and writes to a parameterized number of addresses. The traffic generator also monitors the data read from the memory to ensure it matches the written data and asserts a failure otherwise.
- An I/O PLL to emulate the external core clock that feeds the ext_core_clock port of the HBM2 IP. The clock eventually clocks the Traffic Generator and any other components that are clocked by the wmc_clk_0_clk clock of the HBM2 IP.
Figure 3. Synthesis Design Example
If you enable more than one HBM channel, the synthesis design example includes an additional pair of traffic generators based on how many HBM channels are enabled. Because each HBM channel and HBM pseudo-channel are independent, each of the additional traffic generators are also independent from one another, although connected to a single High Bandwidth Memory (HBM2) Interface Intel FPGA IP. The following figure shows an example with HBM channels enabled.
Figure 4. Synthesis Design Example with Three HBM Channels Enabled
| Signal Group | Signal Name | Direction | Width | Description |
|---|---|---|---|---|
| PLL Ref clk Inputs | core_clk_iopll_ref_clk_clk | Input | 1 | LVDS differential reference clock used by the I/O PLL to generate the fabric core clock. The design example automatically instantiates the I/O PLL that generates the core clock. |
| hbm_0_example_design_pll_ref_ clk_clk | Input | 1 | LVDS differential reference clock used by the UIB PLL. The design example automatically instantiates the UIB PLL that generates the clock for the UIB subsystem. | |
| Resets | core_clk_iopll_reset_reset | Input | 1 | Reset input for the core clock I/O PLL. The reset polarity is active high. Refer to the Intel® Stratix® 10 device datasheet for I/O PLL specifications. |
| hbm_0_example_design_wmcrst_n_ in_reset_n | Input | 1 | General core logic reset; active low. | |
| hbm_only_reset_in_reset | Input | 1 | HBM-only reset; active high. Not currently supported; you can connect this to LOW. | |
| Boundary Scan Signals | m2u_bridge_cattrip | Input | 1 | HBM2 boundary signals that are not driven by the traffic generator. These signals must be exposed at the design example top level to enable successful compilation. These signals should not be actively driven. The Intel® Quartus® Prime software places these signals on pins that are connected to the HBM2 memory. Do not add any location assignments to these pins, as doing so causes compilation errors. |
| m2u_bridge_temp | Input | 3 | ||
| m2u_bridge_wso | Input | 8 | ||
| m2u_bridge_reset_n | Output | 1 | ||
| m2u_bridge_wrst_n | Output | 1 | ||
| m2u_bridge_wrck | Output | 1 | ||
| m2u_bridge_shiftwr | Output | 1 | ||
| m2u_bridge_capturewr | Output | 1 | ||
| m2u_bridge_updatewr | Output | 1 | ||
| m2u_bridge_selectwir | Output | 1 | ||
| m2u_bridge_wsi | Output | 1 | ||
| Traffic Generator Status Signals | tgx_0_status_traffic_gen_pass | Output | 1 | Traffic generator status signals (Pass, Fail and Timeout) for Pseudo Channel 0, per Channel. |
| tgx_0_status_traffic_gen_fail | Output | 1 | ||
| tgx_0_status_traffic_gen_timeout | Output | 1 | ||
| tgx_1_status_traffic_gen_pass | Output | 1 | Traffic generator status signals (Pass, Fail and Timeout) for Pseudo Channel 1, per Channel. | |
| tgx_1_status_traffic_gen_fail | Output | 1 | ||
| t gx_1_status_traffic_gen_timeout | Output | 1 |
Using the Design Example in a Project with Multiple HBM2 Interfaces
Do not instantiate an HBM2 design example in a project multiple times, because a Fitter error may occur.
To create a project with two HBM2 interfaces, create two instances of the HBM2 IP, one with HBM location = Top and one with HBM2 location = bottom. Generate the design example projects for each IP and then instantiate them in the multiple HBM2 interface project.