High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

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ID 683379
Date 4/13/2020
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description 4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
1.1. Release Information
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2 System 2.2. Configuring the High Bandwidth Memory (HBM2) Interface Intel FPGA IP 2.3. IP Parameter Editor Pro Guidelines for High Bandwidth Memory (HBM2) Interface Intel FPGA IP 2.4. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example 2.5. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency 2.6. Generating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example for Simulation 2.7. Regenerating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example After Modification
3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description x
3.1. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Synthesis Design Example 3.2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Simulation Design Example 3.3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Interface tab
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description
4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

2.5. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency

To generate the synthesizable design example with high efficiency in the HBM2 interface and measure the traffic efficiency using the In-System Sources and Probes (ISSP) Editor, follow these steps.
  1. On the Controller tab, deselect the Controller configuration > Enable Reorder Buffer option. The Reorder Buffer rearranges the read data in the order of the issued requests.
  2. On the Diagnostics tab, select Traffic Generator > Force traffic generator to issue different AXI Read/Write IDs. Also, select Performance > Use efficiency pattern.
  3. Set both the Read Count and Write Count values to at least 2500, and select the Sequential option for data traffic Sequence. (Alternatively, if you want to measure the efficiency for traffic with random addresses, set the Sequence option to Random.)
  4. On the Diagnostics tab, select Performance > Enable Efficiency Monitor. Also, select Performance > Enable Efficiency Test Mode. If it is not already checked, check the Enable In-System-Sources-and-Probes checkbox in the Example Design group box.
  5. Click Generate Example Design at the top-right corner of the parameter editor to generate the synthesizable design example.
  6. Apply the specific pinout for the development kit and compile the design.
  7. After the design example is programmed on the circuit board, you can obtain efficiency performance results using the ISSP editor.
  8. Monitor and ensure transactions have completed as indicated by a 1 on the EFFT probe in the In-System Sources and Probes (ISSP) Editor.

    The EFFR 32-bit probe signals can display the value of valid write and read transactions and the total number of active transactions.

    The EFFW is a 3-bit input set source input signal which enables output on the EFFR 32-bit probe signals. The following table shows input values for EFFW and the corresponding EFFR counter output values:

    Table 3.  
    EFFW Source Value Description of EFFR output (32-bits wide)
    3'b 000 Number of valid write data transactions.
    3'b 001 Number of valid read data transactions.
    3'b 010 Total active transaction count.
    3'b 100 Minimum read latency.
    3'b 101 Maximum read latency.

  9. You can calculate efficiency using the following formula, based on the counter values:
    Efficiency=[(Number of Write Data transactions + Number of Read Data transactions accepted by HBM2 controller) ÷ (total active transaction count) × [(core clock frequency) × 2) ÷ (HBM2 interface frequency)] × 100.

    For example, given the following values:

    • Write data transactions: 5000
    • Read data transactions: 5000
    • Total active transactions: 10358
    • Core clock frequency: 250 MHz
    • HBM2 interface frequency: 600 MHz

    Efficiency = [(5000+5000)÷(10358)×(250)×2÷600]×100=80.5%

  10. The traffic generator runs with the efficiency pattern for one test loop by default. To reinitiate the test, reset the HBM2 design example using the ISSP editor. You can use the RSTN signal to reset the HBM2 design example by writing a 0 and then a 1.

Note: For additional information on changing the test duration and traffic pattern for the Intel® Stratix® 10 HBM2 traffic generator, refer to the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Traffic Generator video, available here: https://www.youtube.com/watch?v=XLfw12VCm0U.
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