High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

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ID 683379
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description 4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
1.1. Release Information
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2 System 2.2. Configuring the High Bandwidth Memory (HBM2) Interface Intel FPGA IP 2.3. IP Parameter Editor Pro Guidelines for High Bandwidth Memory (HBM2) Interface Intel FPGA IP 2.4. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example 2.5. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency 2.6. Generating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example for Simulation 2.7. Regenerating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example After Modification
3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description x
3.1. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Synthesis Design Example 3.2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Simulation Design Example 3.3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Interface tab
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description
4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

2.2. Configuring the High Bandwidth Memory (HBM2) Interface Intel FPGA IP

The following steps illustrate the IP Catalog (standalone) configuration flow. The Platform Designer (standalone) flow is generally similar.
  1. Verify that the IP Catalog window is visible. If the IP Catalog window is not visible, select View > Utility Windows > IP Catalog.
  2. In the IP Catalog window, select Installed IP > Library > Memory Interfaces and Controllers > High Bandwidth Memory (HBM2) Interface Intel FPGA IP.
  3. In the New IP Variant window, type a name (<user instance name>) for your HBM2 IP in the File Name field. Click Create.
  4. In the IP Parameter Editor Pro window, configure the parameters on each tab to reflect your Intel FPGA development kit requirement or your actual HBM2 interface and system requirement. For information on individual parameters, refer to the Parameterizing the High Bandwidth Memory (HBM2) Interface Intel FPGA IP section in the High Bandwidth Memory (HBM2) Interface Intel FPGA IP User Guide.
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