High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

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ID 683379
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description 4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
1.1. Release Information
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2 System 2.2. Configuring the High Bandwidth Memory (HBM2) Interface Intel FPGA IP 2.3. IP Parameter Editor Pro Guidelines for High Bandwidth Memory (HBM2) Interface Intel FPGA IP 2.4. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example 2.5. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency 2.6. Generating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example for Simulation 2.7. Regenerating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example After Modification
3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description x
3.1. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Synthesis Design Example 3.2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Simulation Design Example 3.3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Interface tab
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description
4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

2.1. Creating an Intel® Quartus® Prime Project for Your HBM2 System

To create a new IP variation, you must have an open Intel® Quartus® Prime project with a valid device part. If you do not already have an appropriate Intel® Quartus® Prime project, follow these steps to create an Intel® Quartus® Prime project targeting a device that supports High Bandwidth Memory (HBM2) Interface Intel FPGA IP.
  1. Launch the Intel® Quartus® Prime software and select File > New Project Wizard. Click Next.
  2. Specify a directory name (<user project directory>), a name for the Intel® Quartus® Prime project (<user project name>), and a top-level design entity name (<user top-level instance name>) that you want to create. Click Next.
  3. Verify that Empty Project is selected. Click Next two times.
  4. In the Device Family section of the dialog box, select Intel® Stratix® 10 for the Family and Stratix 10 MX for the Device. Alternatively, if you already know the specific part number of the device that you want to use, type that device part number in the Name filter field.
    Note: The generated HBM2 IP targets the specific Intel® Stratix® 10 MX device that you specify. Because different Intel® Stratix® 10 MX part numbers may identify devices with differing numbers of HBM2 devices and differing HBM2 device locations, as well as differing stack count, height, and density properties, it is important that you specify the correct Intel® Stratix® 10 MX device part number before proceeding to the next step.
  5. Select the appropriate device under Available Devices.
  6. Click Finish. The system creates the (<user project directory>).qpf and (<user project directory>).qsf files within the (<user project directory>).
Figure 2. Generated Intel® Quartus® Prime Project and Settings File
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