High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

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ID 683379
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description 4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
1.1. Release Information
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2 System 2.2. Configuring the High Bandwidth Memory (HBM2) Interface Intel FPGA IP 2.3. IP Parameter Editor Pro Guidelines for High Bandwidth Memory (HBM2) Interface Intel FPGA IP 2.4. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example 2.5. Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency 2.6. Generating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example for Simulation 2.7. Regenerating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example After Modification
3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description x
3.1. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Synthesis Design Example 3.2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Simulation Design Example 3.3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Interface tab
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Description
4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

5. Document Revision History for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2020.04.13 20.1 19.4.0 In the HBM2 Design Example Quick Start Guide chapter:
  • In the Configuring the High Bandwidth Memory (HBM2) Interface Intel FPGA IP topic, updated the image in step 4.
  • In the IP Parameter Editor Pro Guidelines for High Bandwidth Memory (HBM2) Interface Intel FPGA IP topic, modified the third bullet in the description of the General tab.
  • In the Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example topic, updated the image in step 1.
  • In the Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency topic, updated the image in step 4.
  • In the Generating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example for Simulation topic, updated the image with step 1 and the text of step 2.
2019.12.12 19.2 19.2.0 Implemented correction to the efficiency example in step 9 of the Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency topic.
2019.08.30 19.2 19.2.0
  • Added About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP.
  • Added Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency topic.
  • Added text to step 2 of the Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example topic.
  • Added text to step 2 of the Generating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example for Simulation topic.
  • Updated the figure in step 4 of Configuring the High Bandwidth Memory (HBM2) Interface Intel FPGA IP.
  • Updated the figures in steps 1 and 3 of Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example.
  • Updated the figures in steps 1 and 3 of Generating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example for Simulation.
2019.05.03 19.1 19.1
  • Modified the Diagnostic description in Table 1, Tab Parameter Guidelines in the IP Parameter Editor Pro Guidelines for High Bandwidth Memory (HBM2) Interface Intel FPGA IP topic.
  • Updated the Diagnostics tab figure and added a step for using the Traffic Generator Use efficiency pattern feature in the Generating the Synthesizable High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example topic.
  • Updated the Diagnostics tab figure and added a step for using the Traffic Generator Use efficiency pattern feature in the Generating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example for Simulation topic.
  • Added High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Design Example User Guide Archives chapter.
2018.12.24 18.1.1 18.1.1 Initial release.
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