3.2. Power-Up Sequence Requirements

Agilex™ 7 Power Management User Guide

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Date 7/08/2024

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3.2. Power-Up Sequence Requirements

The power rails in the Agilex™ 7 devices are divided into three groups.

The following figure shows the voltage groups of the Agilex™ 7 F-Series and I-Series devices and their required power-up sequence.

Figure 2. Power-Up Sequence for the Agilex™ 7 F-Series and I-Series Devices

The following figure shows the voltage groups of the Agilex™ 7 M-Series devices and their required power-up sequence.

Figure 3. Power-Up Sequence for the Agilex™ 7 M-Series Devices

Note: V_CCBAT is not in any of the groups below. V_CCBAT does not have any sequence requirements. V_CCBAT holds the content of the security keys.

For more information about the V_CCBAT connection guidelines and power supply sharing guidelines, refer to the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series .

Table 3. Voltage Rails Group for the Agilex™ 7 F-Series and I-Series Devices
Power Group	FPGA Core and Hard Processor System (HPS)	Additional Voltage Rails
Power Group	FPGA Core and Hard Processor System (HPS)	E-Tile	P-Tile	F-Tile	R-Tile
Group 1	V_CC V_CCP V_CCH V_{CCL_SDM} V_{CCH_SDM} V_{CCPLLDIG_SDM} V_{CCL_HPS} V_{CCPLLDIG_HPS}	V_{CCRT_GXE} V_{CC_HSSI_GXE} ¹ V_{CCRTPLL_GXE}	V_{CC_HSSI_GXP} V_{CCRT_GXP} V_{CCFUSE_GXP}	V_{CC_HSSI_GXF} V_{CCERT_FGT_GXF} V_{CCERT1_FHT_GXF} V_{CCERT2_FHT_GXF}	V_{CC_HSSI_GXR} V_{CCE_PLL_GXR} V_{CCE_DTS_GXR} V_{CCRT_GXR}
Group 2	V_CCPT V_{CCPLL_SDM} V_CCADC V_{CCPLL_HPS}	V_{CCH_GXE} ¹ V_{CCCLK_GXE} ¹	V_{CCH_GXP} V_{CCCLK_GXP}	V_{CCFUSECORE_GXF} V_{CCFUSEWR_GXF} V_{CCCLK_GXF} V_{CCH_FGT_GXF} V_{CCEHT_FHT_GXF}	V_{CCED_GXR} V_{CCCLK_GXR} V_{CCH_FUSE_GXR} V_{CCH_GXR}
Group 3	V_{CCA_PLL} ² V_CCRCORE ² V_{CCIO_PIO_SDM} V_{CCIO_PIO} V_{CCFUSEWR_SDM} V_{CCIO_SDM} V_{CCIO_HPS}	—	—	—	—

All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their respective nominal voltage before the power rails from Group 2 can start ramping up. The power rails within Group 2 can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2 must ramp to a minimum threshold of 90% of their nominal value before the Group 3 power rails can start ramping up. The power rails within Group 3 can ramp up in any order after the last power rail in Group 2 ramps up to a minimum threshold of 90% of their full value. For more information, refer to the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series .

For Agilex™ 7 devices, there is no power-down sequence requirement, except for Agilex™ 7 devices with E-Tile.

For Agilex™ 7 devices without E-Tile, Altera recommends that you reverse the power-up sequence when you power down your device to ensure lowest current draw on each voltage supply.

Table 4. Voltage Rails Group for the Agilex™ 7 M-Series Devices
Group 1	Group 2	Group 3a	Group 3b
V_CC V_CCP V_{CCL_SDM} V_{CCH_SDM} V_CCH V_{CCPLLDIG_SDM} V_{CCL_HPS} V_{CCPLLDIG_HPS} V_{CCLPLL_NOC} V_{CCPLLDIG_NOC}	F-Tile: V_{CCEHT_FHT_GXF}	V_{CCFUSEWR_SDM} V_{CCIO_SDM} V_{CCIO_HPS} V_CCPT V_{CCPLL_NOC} V_{CCIO_NOC} V_{CCPLL_SDM} V_CCADC V_{CCPLL_HPS}	V_{CCIO_PIO} V_{CCN_PIO_SDM} V_CCRCORE V_{CCIO_UIB}
F-Tile: V_{CC_HSSI_GXF} V_{CCFUSECORE_GXF} V_{CCERT_FGT_GXF} V_{CCERT1_FHT_GXF} V_{CCERT2_FHT_GXF} V_{CCFUSEWR_GXF}		F-Tile: V_{CCCLK_GXF} V_{CCH_FGT_GXF}
R-Tile: V_{CC_HSSI_GXR} V_{CCE_PLL_GXR} V_{CCE_DTS_GXR} V_{CCRT_GXR} V_{CCED_GXR} V_{CCCLK_GXR} V_{CCH_FUSE_GXR}		R-Tile: V_{CCH_GXR}
HBM2E: V_{CCM_PUMP_HBM}		R-Tile: V_{CCH_GXR}

All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their respective nominal voltage before the power rails from Group 2 can start ramping up. The power rails within Group 2 can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2 must ramp to a minimum threshold of 90% of their nominal value before the Group 3a power rails can start ramping up. All power rails in Group 3a must ramp to a minimum threshold of 90% of their nominal value before the Group 3b power rails can start ramping up. The power rails within Group 3b can ramp up in any order after the last power rail in Group 3a ramps up to a minimum threshold of 90% of their full value. For more information, refer to the Agilex™ 7 Device Family Pin Connection Guidelines: M-Series .

All power rails must ramp up and ramp down monotonically. The power-up sequence must meet the POR delay time. For the POR specifications of the Agilex™ 7 devices, refer to the POR Specifications section in the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series and Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series .

For configuration via protocol (CvP), the total t_RAMP must be less than 10 ms from the first power supply ramp-up to the last power supply ramp-up. For the t_RAMP specifications, refer to the Recommended Operating Conditions section in the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series and Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series .

¹ For Agilex™ 7 devices with E-Tile, these voltage rails must follow the power-down sequence. For more information, refer to the Power-Down Sequence for the Agilex™ 7 Devices with E-Tile figure.

² For Agilex™ 7 production devices and ES (except 2486A package) devices, V_{CCA_PLL} and V_CCRCORE are part of power Group 3. For Agilex™ 7 ES (2486A package) devices, V_{CCA_PLL} and V_CCRCORE are part of power Group 2.

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Agilex™ 7 Power Management User Guide

3.2. Power-Up Sequence Requirements