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4.3.1. Voltage Monitor Design Guidelines
4.3.2. Temperature Monitor Design Guidelines
4.3.3. Transceiver Tile Local Temperature Sensor Design Guidelines
4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 7 Remote TSD
4.3.5. Guidelines: Reading the R-Tile Local Temperature Sensor
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5.2. DSP and M20K Power Gating
Agilex™ 7 devices support power gating for both DSP blocks and M20K memory blocks. By default, the Quartus® Prime software automatically configures unused DSP blocks and M20K memory blocks to be power gated.