Agilex™ 7 Power Management User Guide

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ID 683373
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Management Overview 2. Agilex™ 7 Power Basics 3. Agilex™ 7 Power and I/O State Sequencing 4. Agilex™ 7 Sensor Monitoring System 5. Agilex™ 7 Power Optimization Techniques and Features 6. Document Revision History for the Agilex™ 7 Power Management User Guide
1. Agilex™ 7 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 7 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 7 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Power-Down Sequence Requirements for Agilex™ 7 Devices with E-Tile 3.4. Power-Down Sequence Requirements for the Agilex™ 7 M-Series Devices 3.5. Floating Voltage 3.6. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in GPIO, HPS, SDM Banks, and UIB Subsystem During Power Sequencing
3.6. Power-On Reset x
3.6.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 7 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations 4.4. Temperature Reading Design Example
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.2.3. Temperature Sensor Locations x
4.2.3.1. Getting Approximate Locations of the Transceiver Banks
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Temperature Monitor Design Guidelines 4.3.3. Transceiver Tile Local Temperature Sensor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 7 Remote TSD 4.3.5. Guidelines: Reading the R-Tile Local Temperature Sensor
4.4. Temperature Reading Design Example x
4.4.1. Directory Structure 4.4.2. Hardware and Software Requirements 4.4.3. Temperature Reading Design Example Description 4.4.4. Using the Temperature Reading Design Example 4.4.5. Verifying the Interaction between the Design Example and the Mailbox Client with Avalon® Streaming Interface IP
4.4.4. Using the Temperature Reading Design Example x
4.4.4.1. Opening the Temperature Reading Design Example 4.4.4.2. Compiling the Temperature Reading Design Example and Generating the Software Object File 4.4.4.3. Programming and Starting Up the Temperature Reading Design Example 4.4.4.4. Sending Commands to the Temperature Reading Design Example
4.4.4.4. Sending Commands to the Temperature Reading Design Example x
4.4.4.4.1. Default Commands for the Temperature Reading Design Example
5. Agilex™ 7 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 7 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 7 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 7 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 7 Power Management Overview
2. Agilex™ 7 Power Basics
3. Agilex™ 7 Power and I/O State Sequencing
4. Agilex™ 7 Sensor Monitoring System
5. Agilex™ 7 Power Optimization Techniques and Features
6. Document Revision History for the Agilex™ 7 Power Management User Guide

3.2.1. Guidelines for I/O Pins in GPIO, HPS, SDM Banks, and UIB Subsystem During Power Sequencing

Agilex™ 7 devices do not support hot-socketing and require a specific power sequence. Design your power supply solution to properly control the complete power sequence.

Adhere to the following guidelines to prevent unnecessary current draw on the I/O pins located in the GPIO, HPS, SDM banks, and UIB subsystem (UIBSS) 3. These guidelines are applicable for unpowered, power up to POR, POR delay, POR delay to configuration, configuration, initialization, user mode, and power down device states.

  • The I/O pins in these banks or subsystem can be in one the following states:
    • GPIO banks—tri-stated, driven to ground, or driven to the VCCIO_PIO level.
    • HPS banks—tri-stated, driven to ground, or driven to the VCCIO_HPS level.
    • SDM banks—tri-stated, driven to ground, or driven to the VCCIO_SDM level.
    • USB subsystem3—tri-stated, driven to ground, or driven to the VCCIO_UIB level.
  • While the Agilex™ 7 device is powering up or down:
    • The input signals of an I/O pin at all times must not exceed the I/O buffer power supply rail of the bank where the I/O pin resides.
    • If you use a pin in a GPIO bank with 1.5 V VCCIO_PIO (for Agilex™ 7 F-Series and I-Series) or 1.3 V VCCIO_PIO (for Agilex™ 7 M-Series), the pin voltage must not exceed the VCCIO_PIO rail or 1.2 V, whichever is lower.
  • While the Agilex™ 7 device is powering up, powering down, or not turned on, the GPIO, SDM, HPS, and UIBSS pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per I/O bank.
  • After the Agilex™ 7 device fully powers up, the voltage levels for the GPIO, SDM, HPS, and UIBSS pins must not exceed the DC input voltage (VI) value.
Table 5.  Guideline Examples for the Agilex™ 7 F-Series and I-Series
Condition Guideline
The VCCIO_SDM pin ramps up and at period X, the VCCIO_SDM voltage is 0.9 V. At period X, keep the signals driven by the device connected to the SDM I/O pin at a voltage of 0.9 V or lower.
The VCCIO_PIO pin ramps up and at period X, the VCCIO_PIO voltage is 1.1 V. At period X, keep the signals driven by the device connected to the GPIO I/O pin at a voltage of 1.1 V or lower.
The 1.5 V VCCIO_PIO pin ramps up and the voltage continues to rise pass the 1.2 V level. Keep the GPIO I/O pin voltage at 1.2 V or lower until the Agilex™ 7 device fully powers up.
Table 6.  Guideline Examples for the Agilex™ 7 M-Series
Condition Guideline
The VCCIO_SDM pin ramps up and at period X, the VCCIO_SDM voltage is 1.8 V. At period X, keep the signals driven by the device connected to the SDM I/O pin at a voltage of 1.8 V or lower.
The VCCIO_PIO pin ramps up and at period X, the VCCIO_PIO voltage is 1.1 V. At period X, keep the signals driven by the device connected to the GPIO I/O pin at a voltage of 1.1 V or lower.
The 1.3 V VCCIO_PIO pin ramps up and the voltage continues to rise pass the 1.2 V level. Keep the GPIO I/O pin voltage at 1.2 V or lower until the F-Series and I-Series device fully powers up.
3 UIB subsystem (UIBSS) is only available in Agilex™ 7 M-Series devices.
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