Agilex™ 7 Power Management User Guide

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ID 683373
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Management Overview 2. Agilex™ 7 Power Basics 3. Agilex™ 7 Power and I/O State Sequencing 4. Agilex™ 7 Sensor Monitoring System 5. Agilex™ 7 Power Optimization Techniques and Features 6. Document Revision History for the Agilex™ 7 Power Management User Guide
1. Agilex™ 7 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 7 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 7 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Power-Down Sequence Requirements for Agilex™ 7 Devices with E-Tile 3.4. Power-Down Sequence Requirements for the Agilex™ 7 M-Series Devices 3.5. Floating Voltage 3.6. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in GPIO, HPS, SDM Banks, and UIB Subsystem During Power Sequencing
3.6. Power-On Reset x
3.6.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 7 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations 4.4. Temperature Reading Design Example
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor Catastrophic Trip Signal 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.2.3. Temperature Sensor Locations x
4.2.3.1. Getting Approximate Locations of the Transceiver Banks
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Temperature Monitor Design Guidelines 4.3.3. Transceiver Tile Local Temperature Sensor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 7 Remote TSD 4.3.5. Guidelines: Reading the R-Tile Local Temperature Sensor
4.4. Temperature Reading Design Example x
4.4.1. Directory Structure 4.4.2. Hardware and Software Requirements 4.4.3. Temperature Reading Design Example Description 4.4.4. Using the Temperature Reading Design Example 4.4.5. Verifying the Interaction between the Design Example and the Mailbox Client with Avalon® Streaming Interface IP
4.4.4. Using the Temperature Reading Design Example x
4.4.4.1. Opening the Temperature Reading Design Example 4.4.4.2. Compiling the Temperature Reading Design Example and Generating the Software Object File 4.4.4.3. Programming and Starting Up the Temperature Reading Design Example 4.4.4.4. Sending Commands to the Temperature Reading Design Example
4.4.4.4. Sending Commands to the Temperature Reading Design Example x
4.4.4.4.1. Default Commands for the Temperature Reading Design Example
5. Agilex™ 7 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 7 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 7 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 7 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 7 Power Management Overview
2. Agilex™ 7 Power Basics
3. Agilex™ 7 Power and I/O State Sequencing
4. Agilex™ 7 Sensor Monitoring System
5. Agilex™ 7 Power Optimization Techniques and Features
6. Document Revision History for the Agilex™ 7 Power Management User Guide

4.2.1. Local Temperature Sensor

The Agilex™ 7 local temperature sensors use built-in 11-bit ADCs and provide temperature readouts through the SDM mailbox.

Each temperature sensor location contains up to two local TSDs in the core fabric, or up to six TSDs in transceiver tiles6.

Figure 8.  Agilex™ 7 FPGAs Local Temperature SensorThis figure is a block diagram of the local temperature sensors. For the physical locations of the sensors, refer to the related information.


Agilex™ 7 devices provide up to 11 local temperature sensor locations for monitoring on-chip temperature.

  • Up to five temperature sensor locations in the core fabric—with a total of up to nine local TSDs among them—allow you to monitor the temperatures around the core fabric.
  • Up to six local temperature sensor locations, one in each transceiver tile, allow you to monitor the temperature of the transceiver tiles. The number of transceiver tiles varies among Agilex™ 7 devices and package options.
  • For M-Series FPGAs, up to two temperature sensor locations, one in each HBM2E tile, allow you to monitor the temperature of the HBM2E tiles. The number of HBM2E tiles varies among the M-Series FPGAs.

Refer to the related information for more details about the locations and availability of the temperature sensors in different Agilex™ 7 series, densities, and packages.

Catastrophic Trip Signal

The catastrophic trip signal, nCATTRIP, is an optional signal that you can assign to any unused SDM_IO pin. If enabled, the nCATTRIP signal transitions high and stays high after the device enters user mode. When the core temperature reaches 120° C and higher, the nCATTRIP signal drives low—you must immediately power down the FPGA to avoid permanent damage to the device. The nCATTRIP signal is only valid after the device enters user mode. Design your system to monitor the nCATTRIP signal only if the FPGA is in user mode and the SDM I/O is configured with the nCATTRIP option enabled in the FPGA design. For example, the FPGA does not enter user mode when being configured using QSPI or the provision helper image; therefore, the nCATTRIP signal should not be monitored in such condition. You must also cease the nCATTRIP signal monitoring when the FPGA reconfiguration is triggered, and resume the nCATTRIP signal monitoring when the FPGA is fully reconfigured.

Note: The catastrophic signal is not supported for the local TSD in the SDM location.
Related Information
6 The number of local TSDs in each location for R-Tile, F-Tile, and E-Tile transceivers are six, five, and four, respectively. Other types of transceiver tiles have only one local TSD per location. For details about availability of the temperature sensors, refer to the related information.
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