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1.1. Migration Considerations
1.2. Software Migration Guidelines
1.3. Specification Comparison
1.4. Evaluating Data Setup and Hold Timing Slack
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices
1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual
1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
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1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
The following trace propagation delay recommendations are applicable when the EPCQ-A device is used.
- For –6 speed grade, the Cyclone® V FPGA tDH specification is 2.5ns.
- The total propagation delay for the DCLK and DATA must be within the following range: 1.0ns < delay for DCLK + DATA < 2.5ns
- Assuming the DCLK and DATA traces have the same length, the DCLK and DATA delay must be within the following range: 0.5ns < delay for DCLK + DATA < 1.25ns
- For –7 and –8 speed grades, the Cyclone® V FPGA tDH specification is 2.9ns.
- The total propagation delay for the DCLK and DATA must be within the following range: 1.4ns < delay for DCLK + DATA < 2.5ns
- Assuming the DCLK and DATA traces have the same length, the DCLK and DATA delay must be within the following range: 0.7ns < delay for DCLK + DATA < 1.25ns
- You must perform IBIS or link simulation to ensure the signal quality is good.