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Ixiasoft
Visible to Intel only — GUID: zpz1578620851827
Ixiasoft
1.5.1.2.2. Example for Simulating the DATA Link
The following three simulation setups are essential to measure the minimum or maximum delay on the DATA signal.
- The setup is used to measure the maximum delay on the DATA signal.
- The maximum flash clock to output delay (tCLQV ) value in the EPCQ-A Serial Configuration Device Datasheet is based on 30pF loading.
- The setup is used to measure the minimum delay on the DATA signal.
- The minimum flash clock to output delay (tCLQX ) value in the EPCQ-A Serial Configuration Device Datasheet is based on 0pF loading.
The maximum DATA delay is calculated by substituting the delay measured between E and C in the simulation into the following equation.
Maximum DATA delay = tCLQV + (delay measurement E – delay measurement C)
Maximum DATA delay = 6ns – 2.343ns
Maximum DATA delay = 3.657ns
The results clearly show that the maximum DATA delay could be smaller depending on the actual system loading which helps to improve the FPGA setup time slack. Using the tCLQV value defined in the EPCQ-A Serial Configuration Device Datasheet is too pessimistic in the setup time analysis.
The minimum DATA delay is calculated by substituting the delay measured between E and D in the simulation into the following equation.
Minimum DATA delay = tCLQX + (delay measurement E – delay measurement D)
Minimum DATA delay = 1.5ns + 0.542ns
Minimum DATA delay = 2.042ns
The results clearly show that the minimum DATA delay could be larger depending on the actual system loading. Using the tCLQX value defined in the EPCQ-A Serial Configuration Device Datasheet is too pessimistic for the hold time analysis.