AN 822: Intel® FPGA Configuration Device Migration Guideline

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ID 683340
Date 4/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Configuration Device Migration Guideline
1. Intel® FPGA Configuration Device Migration Guideline x
1.1. Migration Considerations 1.2. Software Migration Guidelines 1.3. Specification Comparison 1.4. Evaluating Data Setup and Hold Timing Slack 1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices 1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual 1.7. Document Revision History for AN 822: Intel® FPGA Configuration Device Migration Guideline
1.2. Software Migration Guidelines x
1.2.1. IP Core Compatibility 1.2.2. Programming File Compatibility 1.2.3. IP Core and Programming File Migration Guideline 1.2.4. Software Support for EPCQ-A Devices
1.2.3. IP Core and Programming File Migration Guideline x
1.2.3.1. IP Core Regeneration Guideline 1.2.3.2. Programming File Regeneration Guideline
1.3. Specification Comparison x
1.3.1. Operating Conditions 1.3.2. Timing Specifications 1.3.3. Operation Codes 1.3.4. Pin Information 1.3.5. Package Dimensions 1.3.6. Status Register
1.3.2. Timing Specifications x
1.3.2.1. Read Operation Timing 1.3.2.2. Write Operation Timing
1.3.4. Pin Information x
1.3.4.1. 8-pin SOIC Device Pin Information 1.3.4.2. 16-pin SOIC Device Pin Information
1.3.5. Package Dimensions x
1.3.5.1. 8-Pin SOIC Device Package Dimensions 1.3.5.2. 16-Pin SOIC Device Package Dimensions
1.3.6. Status Register x
1.3.6.1. Sector Protect
1.5. Migration Method from EPCQ to EPCQ-A for Arria® V, Cyclone® V, and Stratix® V Devices x
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme
1.5.1. Board Design Guidelines for the Active Serial (AS) Configuration Scheme x
1.5.1.1. IBIS Simulation Example 1.5.1.2. Example for Adding the RC Network on DCLK 1.5.1.3. Example for Adding Buffer on the DCLK 1.5.1.4. Simulating the DCLK Signal at 100 MHz Operation 1.5.1.5. Trace Propagation Delay Recommendation For DCLK Running at a 100-MHz Operation
1.5.1.2. Example for Adding the RC Network on DCLK x
1.5.1.2.1. Example for Simulating the DCLK Link 1.5.1.2.2. Example for Simulating the DATA Link 1.5.1.2.3. Simulation Results
1.5.1.3. Example for Adding Buffer on the DCLK x
1.5.1.3.1. Simulation Results
1. Intel® FPGA Configuration Device Migration Guideline

1.6. Cyclone® V to Cyclone® V QS Device Migration Reference Manual

As flash device manufacturers in the market are moving to new process technology, improved flash memories become faster with shorter delay. This has indirectly cause some challenges in the AS configuration system of the Cyclone® V device to meet the data hold time when migrating to a newer flash device. Therefore, the Cyclone® V QS device which has significantly improved the minimum data hold time requirement in comparison with the non- Cyclone® V QS device has been produced and manufactured. Intel® recommends using the Cyclone® V device with the QS suffix to replace the Cyclone® V device when migrating to a newer or faster flash device.

Note that the Cyclone® V device with the QS suffix part are only available for the following packages:

  • U15 (324 pins)
  • U19 (484 pins)
  • F23 (484 pins)
  • U23 (672 pins)
  • F27 (672 pins)
  • F31 (896 pins)
  • F35 (1152 pins)

The Cyclone® V device with the QS suffix part are not available for the following packages:

  • M11 (301 pins)
  • M13 (383 pins)
  • M15 (484 pins)
  • F17 (256 pins)

To reduce the required minimum data hold time (tDH ) for the AS configuration mode, a longer routing trace is implemented on the DCLK net in the Cyclone® V QS package. The implementation will result in a higher overshoot or undershoot on the DCLK output signal at the receiver, depending on the actual board design. The overshoot or undershoot behavior is an expected behavior in certain combination of driver characteristics, package routing impedance, board design, board trace impedance, and receiver load configuration. The magnitude, slope, and duration of the overshoot or undershoot will depend on the total system transmission line length, impedance discontinuities, board design (serial resistor placement), and load configuration. The anticipated overshoot or undershoot behavior is within the overshoot or undershoot level and the duration permitted by the Intel® FPGA configuration device (EPCQ-A) and third-party configuration devices supported by Intel® . You can perform IBIS simulation based on the DCLK operating frequency and your system setup to ensure the overshoot or undershoot level and the duration are within the specifications permitted by the configuration device when migrating to a Cyclone® V QS package.

The following steps are the manual intervention required to setup the IBIS simulation deck and to simulate the active serial interfaces for the Cyclone® V QS package.

  1. Use the Cyclone® V IBIS model and the S-parameter file for the QS package. You can download the S-parameter file for the Cyclone® V QS package using the Cyclone® V IBIS Models (cyclone5.zip) from the IBIS Models for Intel® Devices page provided on the Related Information section below.
    Figure 28.  Cyclone® V QS IBIS Model with the S-parameter File
  2. Manually set the package-lumped RLC and per pin RLC for the active serial interfaces to zero in the Cyclone® V IBIS model.

IBIS Simulation for the Cyclone® V QS Package when Interfacing with Intel® EPCQ128ASI16N Model

Figure 29. Overshoot/Undershoot Observed on the DCLK Signal with DCLK Operating at 50MHz
  • The overshoot or undershoot level is within the transient voltage specification stipulated in the Absolute Maximum Rating Specification for EPCQ-A Devices in the EPCQ-A Serial Configuration Device Datasheet.
  • Blue signal: Simulation with non- Cyclone® V QS package.
  • Green signal: Simulation with Cyclone® V QS package.

In the event of violating the overshoot or undershoot level permitted by the configuration device, Intel® recommends you to add series termination resistor at the source side of the DCLK pin to reduce the overshoot or undershoot of the DCLK signal. Adding the series termination is essential to ensure the source side is terminated with the same impedance that matches the transmission line impedance. Although adding the series termination helps to reduce the overshoot or undershoot on the DCLK, this in turn has some drawbacks that increases the propagation delay and the rise or fall time of the signal. Therefore, you must re-analyze the AS configuration system timing to ensure the setup and hold time meets the requirements stipulated in the Cyclone® V FPGA Device Datasheet.

Related Information
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