Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Avalon Memory-Mapped CPU interface Avalon Memory-Mapped Memory interface Clocking Resets Interrupts Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

Warp IP Interfaces

The Warp IP has four functional interfaces.

The functional interfaces are:

  • Intel FPGA video stream input interface
  • Intel FPGA video stream output interface
  • Avalon Memory-Mapped compatible CPU interface
  • Avalon Memory-Mapped compatible memory interface

Avalon Memory-Mapped CPU interface

The Warp IP control interface uses a 32bit Avalon Memory-Mapped interface to access control registers.

Table 59.   Avalon Memory-Mapped CPU interface Signals
Signal name Direction Width Description
av_mm_control_agent_address Input 13 The byte address of the register being accessed.
av_mm_control_agent_write Input 1 Assert to indicate a write transfer.
av_mm_control_agent_byteenable Input 4 Enables one or more byte lanes during a write transfer.
av_mm_control_agent_writedata Input 32 Data for write transfers.
av_mm_control_agent_read Input 1 Assert to indicate a read transfer.
av_mm_control_agent_readdata Output 32 Data for read transfers.
av_mm_control_agent_readdatavalid Output 1 Asserted by the IP to indicate valid read data.
av_mm_control_agent_waitrequest Output 1 Asserted by the IP to indicate that the host must wait to complete the transfer.

Avalon Memory-Mapped Memory interface

The Warp IP memory interface uses a 512-bit Avalon Memory-Mapped interface to access external memory.

Signal name Direction Width Description
av_mm_memory_host_waitrequest Input 1 Asserted by the agent to indicate that the Warp IP must wait to complete the transfer.
av_mm_memory_host_readdata Input 512 Data for read transfers.
av_mm_memory_host_readdatavalid Input 1 Assert to indicate valid read data.
av_mm_memory_host_response Input 2 The response status of the agent.
av_mm_memory_host_burstcount Output 4 Indicates the number of transfers in each burst.
av_mm_memory_host_writedata Output 512 Data for write transfers.
av_mm_memory_host_address Output 32 The byte address of the memory location being accessed.
av_mm_memory_host_write Output 1 Asserted to indicate a write transfer.
av_mm_memory_host_read Output 1 Asserted to indicate a read transfer.
av_mm_memory_host_byteenable Output 64 Enables one or more byte lanes during a write transfer.
av_mm_memory_host_debugaccess Output 1 Not used by the Warp IP.

Clocking

The Warp IP has five clock domains, each with a corresponding reset. All clock domains run up to 300 MHz.

Table 60.  Clock Domains
Clock name Description
av_mm_control_agent_clock CPU interface clock domain
av_mm_memory_host_clock Memory interface clock domain
axi4s_vid_in_0_clock Input video stream clock domain
axi4s_vid_out_0_clock Output video stream clock domain
core_clock Processing engine clock domain

The CPU interface uses little bandwidth and does not impose a minimum clock frequency.

The video clock frequency depends on the video resolution and frame rate and the Warp IP’s number of pixels in parallel. For example, a 300 MHz clock at 2 pixels in parallel supports active video resolutions up to 3840x2160 at 60 fps. A 150 MHz clock at 1 pixel in parallel supports resolutions up to 1920x1080 at 60 fps.

All RTL-based blocks that transfer or receive data from a different clock domain include clock domain crossing (CDC) circuits for both, single bit and data bus signal cases. The CDC circuits safely allow exchange of data between the two asynchronous clock domains. The Warp IP includes an .sdc file to constrain these CDC paths.

Resets

Table 61.  Resets associated to clock domainsAll resets are synchronous active-high
Reset name Description
av_mm_control_agent_reset CPU interface clock domain reset.
av_mm_memory_host_reset Memory interface clock domain reset.
axi4s_vid_in_0_reset Input video stream clock domain reset.
axi4s_vid_out_0_reset Output video stream clock domain reset.
core_reset Processing engine(s) clock domain reset.

All the resets in the Warp IP are synchronous. Ensure that, when resetting the Warp IP, all clocks are active at the same time while you apply the resets. In a typical system, an EMIF IP block drives and controls these signals. The relationship between the various resets and clocks is not always obvious.

Interrupts

Table 62.  Interrupt Signals
Signal Description
interrupt_irq

Active high interrupt triggered at the start of each output frame sent from the axi4s_vid_out_0 interface. The signal is synchronous to the av_mm_control_agent_clock domain.

Enable tinterrupt_irq using the interrupt control register and clear using the interrupt status register.

Related Information
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