Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

Protocol Converter Intel® FPGA IP Functional Description

Protocol Converter - Avalon Streaming Video to Intel FPGA Streaming Video

The IP converts the protocol in steps:

  1. Changes the Avalon Streaming ready latency from 1 to 0.

    Avalon Streaming Video specifies a ready latency of 1. The IP converts the ready latency to 0 to match the ready-valid handshake mechanism specified for AXI4-Stream.

  2. Removes all non-video data packets from the stream.

    Avalon Streaming Video specifies a mechanism to assign a type identifier (a number between 0 and 15) to each packet in the stream. Type-0 packets are frames of pixel data and all other packet types indicate non-video data. Packets of type-15 (referred to as control packets) contain metadata to specify the width, height, and interlacing properties of subsequent type-0 video packets. Intel FPGA Streaming Video does not allow for nonvideo packets in the stream. The IP discards all packets with a type that is greater than 0. The IP does not propagate type-15 control packets that specify the properties of the video. However, it parses them during the discard process to extract the expected width of the video frames that follow. The IP uses this information in the next step of the conversion.

  3. Splits frame packets into line packets.

    Avalon Streaming Video specifies that each video packet contains one cycle of header data followed by all of the pixels required for an interlaced or progressive frame of video. The header data specifies the packet type. Intel FPGA Streaming Video requires that each packet is one line of video data (with no header information). The IP strips out incoming Avalon Streaming Video frame packets and then splits them into multiple packets. Each packet contains a single video line. The IP extracts the expected width of the video frame from the discarded control packet that precedes the frame. The IP uses this value to determine where the incoming frame packet should be split to make each output line packet. The IP replaces the Avalon Streaming startofpacket and endofpacket signals by the AXI4-Stream tlast signal and creates the tuser signal. The IP reformats the incoming Avalon Streaming data to create byte aligned AXI4-Stream tdata

Protocol Converter - Intel FPGA Streaming Video to Avalon Streaming Video

The IP converts the protocol in 3 steps.

  1. Combines line packets into a single frame packet.

    Intel FPGA Streaming Video specifies that you transmit video data with one video line per packet. Avalon Streaming Video requires you transmit all the pixels in a frame in a single packet. The incoming line packets must merge to form one frame packet. If you transmit a single pixel per clock cycle, bit 0 of the incoming tuser signal marks the first pixel of each frame. The IP concatenates packets until bit 0 of tuser is asserted. If the number of pixels per line is not a multiple of the pixels per clock, the extra pixels in the final clock cycle of data are effectively empty and you must ignore them. You must specify the width of the incoming video frame via the register map. The IP uses this width information to determine which (if any) pixels it should ignore at the end of each line when concatenating the packets.

  2. Adds the frame packet header and the control packet

    Avalon Streaming Video requires that each frame packet begins with a one cycle header specifying a packet type of 0. The IP adds this header to the frame packet created previously. Avalon Streaming Video also recommends that each frame packet is preceded by a control packet (of type-15) that specifies the width, height, and interlacing scheme of the following frame. You supply the width and height via the register map, as the initial value for interlacing specifier. The IP uses these values to control Avalon Streaming control packets that it adds to the stream. If you select an interlacing specifier for progressive video, the IP uses this value for all control packets. If the interlacing specifier identifies an interlaced scheme, the IP toggles the f0/f1 bit automatically in the outgoing control packets.

  3. Converts Avalon Streaming ready latency 0 to 1

    The IP replaces the AXI4-Stream tlast signal with the Avalon Streaming startofpacket and endofpacket signals. The IP creates the empty signal (if the number of pixels per clock cycle is greater than 1). The IP reformats the AXI4-Stream byte aligned tdata to non-byte aligned Avalon Streaming data. The interface is now compliant to the Avalon Streaming protocol, but with a ready latency of 0. Avalon Streaming Video requires that the ready latency is 1, so the IP converts the ready latency from 0 to 1.

Pixel data format

The pixel data format for Avalon Streaming Video and Intel FPGA Streaming Video is almost identical. Intel FPGA Streaming Video requires that the width of each pixel is rounded up to the next whole number of bytes. Any extra bits required can be filled with zeros, ones, or any random data. Avalon Streaming Video has no such requirement and uses only the required bits for each pixel. The Protocol Converter adds the required extra bits when converting from Avalon Streaming Video to Intel FPGA Streaming Video. It removes them when converting from Intel FPGA Streaming Video to Avalon Streaming Video.

Avalon Streaming Video and Intel FPGA Streaming Video both specify how the color planes in each pixel should be arranged for RGB and YCbCr formatted data. For YCbCr data, the protocols specify the color plane ordering for 4:4:4, 4:2:2 and 4:2:0 chroma sampling. The color plane ordering is almost identical between the two protocols, apart from the Y and Cr planes are swapped in the case of YCbCr 4:4:4. The Protocol Converter IP can implement the swap, but you must specify the color space and chroma sampling for each frame. You can specify either via the parameters or the register map accessed through an Avalon memory-mapped agent interface.

You can turn on or turn off the Avalon memory-mapped agent interface via a parameter. If the Avalon memory-mapped agent interface is turned on, specify the color space and chroma sampling at run time via the register map. If the Avalon memory-mapped agent interface is not turned on, specify the color space and chroma sampling in the Video color space and Video chroma sampling parameters respectively.

If the Protocol Convert IP converts from Intel FPGA Streaming Video to Avalon Streaming Video, turn on the Avalon memory-mapped agent interface and do not use the parameters. If the Protocol Convert IP converts from Avalon Streaming Video to Intel FPGA Streaming Video, the Avalon memory-mapped agent interface is optional. If you know the color space and chroma sampling are fixed for the system, you can opt to turn off the agent interface and specify the color space and chroma sampling via the parameters. If the color space and chroma sampling may vary at run time, turn on the agent interface and specify the values in the register map.

For conversions both ways, the IP gates the color plane swap for YCbCr 4:4:4 formatted data by the YCbCr 444 colour swap parameter. You must turn on this option for the IP to apply the color plane swap.

Control packet width for 4:2:0 chroma sampled video

When you transmit 4:2:0 chroma sampled data across an Avalon Streaming Video interface, the frame width that the control packet reports is always half the actual frame width. Each section of the bus contains two luma samples that Avalon Streaming Video regards as a pixel. The value that the control packet reports is relative to a single pixel in each of these sections of the bus. If you specify the chroma sampling of the incoming video, the control panel reports the double-packing of luma samples in 4:2:0 chroma sampling.

End of frame detection

Intel FPGA Streaming Video does not explicitly mark the end of each frame. For Avalon Streaming Video, the endofpacket signal marks the end of each video frame that is asserted on the final pixel of the video data packet.

In Avalon Streaming Video, you cannot transmit the final pixel of each frame until you are certain that it is the final pixel, otherwise you risk driving the endofpacket signal incorrectly.

For Intel FPGA Streaming Video the end of each frame is inferred by receiving the start-of-frame marker for the next frame, which is explicitly indicated in the protocol. You might see potential latency issues when converting from Intel FPGA Streaming Video to Avalon Streaming Video. The IP cannot transmit the final pixel of reach frame at the output until it receives the first pixel of the next frame at the input.

If the video application has no significant blanking (delay) between the last pixel of one frame and the first pixel of the next frame, the IP gives little or no delay in sending out the final pixel of each frame. If the application does have significant blanking, the delay to transmit the final pixel may be too long. The Protocol Converter IP includes an option to remove this delay.

If you turn on Low latency mode, the Protocol Converter IP transmits the Avalon Streaming Video frame endofpacket according to the number of lines it expects in each frame, as you specify in the register map. The Intel FPGA Streaming Video protocol transmits each line of video data as a packet, so the IP terminates the output frame at the end of the input packet for the specified number of lines. If the IP receives any additional lines, the IP discards them and does not transmit them at the output.

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