Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

3D LUT IP Block Description

The 3D LUT IP accepts RGB-format video input from its Intel FPGA video streaming interface. It uses the most significant bits (MSBs) of the 3 color component inputs to retrieve data values from the contents of the LUT and the least significant bits (LSBs) to interpolate the final output value. An Avalon Memory-Mapped compatible CPU interface handles the run-time control and LUT programming.
Figure 4. 3D LUT IP block diagram

The address decoder converts the MSBs of the three input color components into read addresses for the LUT. If you turn on Double buffered, the IP adds a page offset to the address when selecting the second buffer via the CPU interface. Page-flip double buffering allows for instantaneous switching between LUTs.

The LUT RAM instantiates the on-chip memory containing the LUT. The 3D LUT cube vertices are divided across eight sub-RAMs to output the target sub-cube vertices in parallel. Enabling the second buffer doubles the memory depth of the LUT. Both buffers' contents are programmable via the CPU interface and can also be pre-initialized in the firmware via the 3D LUT IP GUI.

The tetrahedral interpolator uses a DSP efficient method to interpolate four of the LUT subcube vertices using the input LSBs. Part of the input MSBs determines which of the six tetrahedra in the target sub-cube contains the pixel.

The control register in the run-time control register map allows you to switch between the interpolated output and the bypass output.

Consider these points when integrating in a streaming video pipeline:

  • The IP controls buffer selection and output enable and only updates them at the start of each new frame.
  • The internal pipeline forwards control signals and is unaffected by changes to video resolution.
Figure 5. 3D LUT color transform examplesFrom top left: original, saturation, brightness increase, colorize (purple), colorize (green), desaturation
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