Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

TMO IP Registers

The TMO IP allows run-time configuration parameters via AXI4-Lite CPU register interface.

The IP offers the following categories of run-time configuration parameters:

  • Flow control parameters that allow you to put the TMO IP into either reset, bypass, or operational mode.
  • Status and debug parameters that provide information about compile-tile parameters and on-the flight status of the TMO IP
  • Video configuration parameters that allow you to configure the input video frame geometry
  • Image statistics collection parameters that allow you to configure the tile’s dimension
Table 41.  Register Map
Register Name Byte Address Offset Access Type
vid_pid 0x000

RO
version_number 0x004

RO
reserved_area 0x140 – 0x147 Reserved
ip_information_0 0x148

RO
ip_information_1 0x14C

RO
ip_information_2 0x150

RO
vid_flow_control 0x154

RW
actv_vid_size 0x158

RW
volume_control 0x15C

RW
tmo_derived_parameters 0x160 – 0x17F

Reserved.
Table 42.   vid_pid
Bits Description

31:0

 Product Identification Number.
Table 43.   version_number
Bits Description

31:0

 Version Number.
Table 44.   reserved_area
Bits Description

31:0

 Reserved register area
Table 45.   ip_information_0
Bits Description

27:24

Number of tiles (C_TILE)

23:16

AXI4-Stream data width

11:8

Pixels in parallel (C_PIXELS)

7:4

Components per sample (C_STREAMS)

3:0 Bits per component (C_DEPTH)
Table 46.   ip_information_1
Bits Description

29:25

Fractional precision for luminance weights (C_FRAC_PREC_MLUT)

24:20

Fractional precision for TMO volume control (C_FRAC_PREC_VOLCNTR)

19:15 Fractional precision for RGB to luma conversion (C_FRAC_PREC_RGB2LUMA)

14:10

 Fractional precision for luma to RGB conversion (C_FRAC_PREC_LUMA2RGB)
9:5

Histogram address data width (C_HIST_ADDR_WIDTH)

4:0

Histogram data width (C_HIST_DATA_WIDTH)

Table 47.   ip_information_2
Bits Description

21:17

 Fractional precision for interpolation (C_FRAC_PREC_INTP)

16:12

 Fractional precision for histogram equalization (C_FRAC_PREC_HEQ)
11:0

Fractional precision for histogram normalization factor (C_NORM_FACT)

Table 48.   vid_flow_control
Bits Description
31

Soft-reset bit. When set to 1 the TMO IP is in reset.
0

Passthrough bit. When set to 1, the TMO IP is in bypass mode, i.e. it does not perform any tone mapping operation on the input images.

Table 49.   actv_vid_size
Bits Description

29:16

Total number of active pixels per video line (C_WIDTH)

13:0

Total number of active lines per video frame (C_HEIGHT)

Table 50.   volume_control
Bits Description

22:16

Fine-level TMO volume control. Valid range [0:100] decimal

13:0

 Coarse-level TMO strength threshold. Valid range [0:9000] decimal
Table 51.   tmo_derived_parameters
Bits Description

31:0

 This area is reserved for all derived parameter registers. Do not write or read from it.
Level Two Title