Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

About the Tone Mapping Operator IP

The tone mapping operator (TMO) Intel FPGA IP dynamically adapts the processing of an image based on a regional (i.e. tile based) approach. It improves the visibility of latent image detail and enhances the overall viewing experience.

You can configure the required number of bits per symbols, symbols per pixel, and pixels in parallel. Typical applications include:

  • Medical imaging
  • Machine vision
  • Video conferencing
  • Surveillance
  • Automotive imaging
Figure 7.  Example of processing a real-life image using the TMO IPThe figure shows example results obtained after applying the TMO IP dataflow on a real-life image: left is the original image; right is the output image after TMO IP processing.

You provide and receive video data to the TMO IP in RGB format via the AXI4-Stream video interfaces. The IP determines the size of the video busses from the number of pixels processed per clock cycle, the color bit depth, and the number of component streams parameters. The number of video component streams is fixed at 3. The IP supports:

  • Component bit depths of 8, 10 and 12-bit.
  • Pixels per clock of 1, 2 and 4.

You control the strength of the contrast enhancement for the output images provided by the TMO IP via an Avalon memory-mapped control interface. The data bus for the control interface is set to 32-bit to interface with an embedded CPU. During operation, you can configure the TMO IP using a software driver that controls all the IP parameters via a set of software APIs .

The TMO IP supports RGB sampling. The sampling method at the output is always the same as the input. You must provide details of the current standard video resolution via the CPU control interface to ensure correct behavior. the IP only supports 4:4:4 progressive sampling. You should prerform any deinterlacing and chroma up or down sampling externally to the TMO IP.

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