Video and Vision Processing Suite Intel® FPGA IP User Guide

Download PDF
ID 683329
Date 9/30/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

3D LUT IP Parameters

The 3D LUT IP offers compile-time parameters.
Table 12.  3D LUT IP compile-time parameters
Name Values Description
Video data format
Number of pixels in parallel 1 to 8 Number of pixels transmitted every clock cycle.
Input bits per color sample 8 to 16 Number of bits per color sample at the input.
Output bits per color sample 8 to 16 Number of bits per color sample at the output.
Control settings
Separate clock for control interface On or off Turn on to run the run-time control interface on a different clock domain.
LUT read interface On or off Allows you to read LUT contents via the CPU interface.
Enabled out of reset On or off
  • Turn on to enable the LUT out of reset
  • Turn off to bypass the LUT out of reset
LUT settings
Size 9, 17, 33, 65 Size of each LUT dimension.
Bits per color 8 to 16 The number of bits per color in the LUT (LUT_DEPTH).
Output alpha channel On or off

Turn on to add alpha channel to the LUT (RGBA).
Bypass alpha 0 to 2 LUT_DEPTH -1 The alpha value output in bypass mode.
Double buffered On or off

Double the memory for seamless LUT programming and switching:

  • On to instantiate the second buffer
  • Off for single buffer only
Buffer 0 and Buffer 1
Initialize from file On or off Turn on to initialize the LUT from the initialization file.
Init file user file Optional initialization file.
Init file type normalized, integer

Type of coefficients in the initialization file:

  • Normalized floating- or fixed-point numbers between 0.0 and 1.0
  • Integer numbers between 0 and 2 LUT_DEPTH -1
Figure 3. 3D LUT GUI

LUT Initialization File

You can initialize each buffer of the LUT from reset by providing a compatible 3D LUT file to Init file in the GUI. The IP generation process converts the LUT file into RAM initialization .hex files that get built into the firmware during compilation. The script can read .cube format files, or any 3D LUT files that follow these conventions:

  • RGB component order (must match the video stream’s order)
  • Components change first from left to right, i.e. R first, G second, B third
  • If you turn on alpha, you append the alpha value as a fourth component (RGBA)
  • The data type must match the IP GUI parameter and may either be:
    • normalized fixed- or floating-point numbers between 0.0 to 1.0
    • integers between 0 and 2LUT_DEPTH-1 (e.g. 10-bit: 0 to 1023)
  • The data type must be the same for the whole file
  • Lines starting with # or any letter are ignored
Level Two Title