Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

3D LUT IP Performance IP and Resource Information

Intel provides resource and utilization data for guidance.
Table 11.  3D LUT Performance and Resource UsageThe numbers are for a design targeting an Intel Arria 10 device with a design fMAX of 300 MHz.
Pixel in parallel Bits per color sample LUT Size Double buffer ALMs Memory (M20K) DSP Blocks
1 8 17 no 810 17 6
1 8 17 yes 937 25 6
2 10 17 no 1,640 33 12
2 10 17 yes 1,681 49 12
2 10 33 no 1,649 120 12
2 10 33 yes 1,685 224 12
2 10 65 no 2,575 830 12
2 10 65 yes 4,035 1,622 12
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