Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

Protocol Converter Intel® FPGA IP Interfaces

Table 7.  Protocol Converter InterfacesThe table lists the interfaces used by the IP. The IP does not enable all interfaces in all parameterizations. The table shows the parameter settings for which the IP enables each interface.
Interface name Clock domain Signals Description
main_clock n/a main_clock_clk Main clock used to drive the IP logic and streaming interfaces
main_reset main_clock main_reset_reset Main reset that initializes the IP logic and streaming interfaces
agent_clock n/a agent_clock_clk Only enabled if you turn on Separate clock for control interface. The clock that drives the av_mm_control_agent interface
agent_reset agent_clock agent_reset_reset Only enabled if you turn on Separate clock for control interface. The reset that initializes the av_mm_control_agent interface
av_mm_control_agent main_clock or agent_clock

av_mm_control_agent_read

av_mm_control_agent_write

av_mm_control_agent_address

av_mm_control_agent_byteenable

av_mm_control_agent_waitrequest

av_mm_control_agent_readdata

av_mm_control_agent_readdatavalid

av_mm_control_agent_writedata

Only enabled if you turn on the Memory mapped control interface. The Avalon memory-mapped agent interface that you use to edit settings in the register map at run time. Clocks on the agent_clock domain if you turn on Separate clock for control interface, otherwise clocks on the main_clock domain
axi4s_vid_in main_clock

axi4s_vid_in_tvalid

axi4s_vid_in_tready

axi4s_vid_in_tlast

axi4s_vid_in_tuser

axi4s_vid_in_tdata

Only enabled if you select Intel FPGA Streaming Video for the Input protocol variant. Intel FPGA Streaming Video compliant streaming sink
av_st_vid_in main_clock

av_st_vid_in_valid

av_st_vid_in_ready

av_st_vid_in_startofpacket

av_st_vid_in_endofpacket

av_st_vid_in_data

av_st_vid_in_empty

Only enabled if the Input protocol variant parameter is set to Avalon Streaming Video. Avalon Streaming Video compliant streaming sink
axi4s_vid_out main_clock

axi4s_vid_out_tvalid

axi4s_vid_out_tready

axi4s_vid_out_tlast

axi4s_vid_out_tuser

axi4s_vid_out_tdata

Only enabled if the Output protocol variant parameter is set to Intel FPGA Streaming Video Lite. Intel FPGA Streaming Video compliant streaming source
av_st_vid_out main_clock

av_st_vid_out_valid

av_st_vid_out_ready

av_st_vid_out_startofpacket

av_st_vid_out_endofpacket

av_st_vid_out_data

av_st_vid_out_empty

Only enabled if you select Avalon Streaming Video in the Input protocol variant. Avalon Streaming Video compliant streaming source
Related Information
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