Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

Protocol Converter Intel® FPGA IP Parameters

The IP offers compile-time parameters
Table 6.  ParametersThe table lists the parameters that are available to configure the IP in Platform Designer.
Name Values Description
Bits per color sample 8 to 16 Number of bits that represent each color sample
Number of color planes 1 to 4 Number of colors per pixel
Number of pixels in parallel 1, 2, 4 or 8 Number of pixels transmitted per clock cycle
YCbCr 444 colour swap On or off Turn on to automatically correct for the color plane ordering differences between Avalon Streaming Video and Intel FPGA Streaming Video when transmitting YCbCr data with 4:4:4 chroma
Memory mapped control interface On or off Turn on to allow the Avalon memory-mapped control agent interface to update settings at run time
Separate clock for control interface On or off Turn on for a separate clock domain for the Avalon memory-mapped control agent interface
Debug features On or off Turn on for the debugging features of the Avalon memory-mapped control agent interface
Pipeline ready signals On or off Turn on to add extra pipeline registers to the AXI4-Stream or Avalon Streaming ready signals. Turning on this option may make it easier to close timing for the protocol converter and achieve a higher operation clock frequency, but may contribute to additional ALM usage.
Input protocol variant Avalon Streaming Video or Intel FPGA Streaming Video Lite Select the protocol for the input interface
Output protocol variant Avalon Streaming Video or Intel FPGA Streaming Video Select the protocol for the output interface
How Avalon-ST Video user packets are handled No user packets expected at the input or Discard all user packets received Select how user packets are handled if the input protocol is Avalon Streaming Video. If you do not expect the input stream to contain any user packets, you can select No user packets expected at the input and save the ALM resources required to discard these packets
Video color space RGB or YCbCr If the input protocol is Avalon Streaming Video and you do not turn on Avalon memory-mapped control agent interface, you must specify the color space of the incoming video
Video chroma sampling 444, 422 or 420 If the input protocol is Avalon Streaming Video and you turn off Avalon memory-mapped control agent interface, you must specify the chroma sampling of the incoming video
Enable low latency mode On or off If the input protocol is Intel FPGA Streaming Video this parameter determines the behaviour of the Protocol Converter at the end of each video frame.
Figure 2. Protocol Converter GUI
Level Two Title