Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 9/30/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Compilation 2. Reducing Compilation Time 3. Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Design Analysis & Elaboration 1.3. Design Synthesis 1.4. Design Place and Route 1.5. Incremental Optimization Flow 1.6. Fast Forward Compilation Flow 1.7. Full Compilation Flow 1.8. HSSI Dual Simplex IP Generation Flow 1.9. Exporting Compilation Results 1.10. Clearing Compilation Results 1.11. Integrating Other EDA Tools 1.12. Compiler Optimization Techniques 1.13. Compilation Monitoring Mode 1.14. Viewing Quartus Database File Information 1.15. Understanding the Design Netlist Infrastructure 1.16. Using Synopsys* Design Constraint (SDC) on RTL Files 1.17. Using the Node Finder 1.18. Synthesis Language Support 1.19. Synthesis Settings Reference 1.20. Fitter Settings Reference 1.21. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy 1.1.3. Using the Compilation Dashboard
1.2. Design Analysis & Elaboration x
1.2.1. Locating Design Elements 1.2.2. Using the RTL Analyzer
1.2.1. Locating Design Elements x
1.2.1.1. Copying Hierarchy Path Names
1.2.2. Using the RTL Analyzer x
1.2.2.1. Sweep Hints Viewer 1.2.2.2. Object Set Console 1.2.2.3. Module Interfaces 1.2.2.4. Bundled Instances 1.2.2.5. Auto-hide Unconnected Pins 1.2.2.6. Filtering Ports and Nets 1.2.2.7. Expand Connections
1.3. Design Synthesis x
1.3.1. Preparing for Design Synthesis 1.3.2. Running Synthesis 1.3.3. Post-Synthesis Static Timing Analysis (STA) 1.3.4. Viewing Synthesis Reports
1.3.2. Running Synthesis x
1.3.2.1. Preserving Registers During Synthesis 1.3.2.2. Preserving Signals for Monitoring and Debugging
1.3.4. Viewing Synthesis Reports x
1.3.4.1. Viewing IP Core License Data 1.3.4.2. Viewing Synthesis Dynamic Report
1.4. Design Place and Route x
1.4.1. Running the Fitter 1.4.2. Viewing Fitter Reports
1.4.1. Running the Fitter x
1.4.1.1. Fitter Commands 1.4.1.2. Disabling or Enabling Physical Synthesis Optimization
1.4.2. Viewing Fitter Reports x
1.4.2.1. Plan Stage Reports 1.4.2.2. Place Stage Reports 1.4.2.3. Route Stage Reports 1.4.2.4. Retime Stage Reports 1.4.2.5. Finalize Stage Reports
1.4.2.2. Place Stage Reports x
1.4.2.2.1. Global Signal Visualization Report
1.4.2.3. Route Stage Reports x
1.4.2.3.1. Global Router Congestion Hotspot Summary Report 1.4.2.3.2. Global Router Wire Utilization Map Report
1.5. Incremental Optimization Flow x
1.5.1. Concurrent Analysis During Synthesis or Fitting 1.5.2. Analyzing Compiler Snapshots 1.5.3. Validating Periphery (I/O) after the Plan Stage
1.5.2. Analyzing Compiler Snapshots x
1.5.2.1. Running Snapshot Viewer
1.5.2.1. Running Snapshot Viewer x
1.5.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.5.2.1.2. Analyzing Clocking with Snapshot Viewer 1.5.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.5.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.5.2.1.5. Analyzing Congestion with Snapshot Viewer
1.6. Fast Forward Compilation Flow x
1.6.1. Step 1: Run Register Retiming 1.6.2. Step 2: Review Retiming Results 1.6.3. Step 3: Run Fast Forward Compile 1.6.4. Step 4: Review Fast Forward Results 1.6.5. Step 5: Implement Fast Forward Recommendations 1.6.6. Retiming Restrictions and Workarounds
1.6.2. Step 2: Review Retiming Results x
1.6.2.1. Locate Critical Chains
1.6.3. Step 3: Run Fast Forward Compile x
1.6.3.1. Fast Forward Compile By Hierarchy 1.6.3.2. HyperFlex Settings
1.6.4. Step 4: Review Fast Forward Results x
1.6.4.1. Clock Fmax Summary Report 1.6.4.2. Fast Forward Details Report
1.7. Full Compilation Flow x
1.7.1. Full Compilation Flow with Temporary Optimization Mode
1.9. Exporting Compilation Results x
1.9.1. Exporting a Version-Compatible Compilation Database 1.9.2. Importing a Version-Compatible Compilation Database 1.9.3. Creating a Design Partition 1.9.4. Exporting a Design Partition 1.9.5. Reusing a Design Partition
1.11. Integrating Other EDA Tools x
1.11.1. Generating a VQM Netlist for other EDA Tools
1.12. Compiler Optimization Techniques x
1.12.1. Compiler Optimization Modes 1.12.2. Allow Register Retiming 1.12.3. Automatic Gated Clock Conversion 1.12.4. Enable Intermediate Fitter Snapshots 1.12.5. Fast Preserve Option 1.12.6. Fractal Synthesis Optimization
1.12.6. Fractal Synthesis Optimization x
1.12.6.1. Enabling or Disabling Fractal Synthesis
1.14. Viewing Quartus Database File Information x
1.14.1. QDB File Attribute Types
1.15. Understanding the Design Netlist Infrastructure x
1.15.1. DNI Netlist Five-Box Data Model
1.15.1. DNI Netlist Five-Box Data Model x
1.15.1.1. Use Case Examples
1.15.1.1. Use Case Examples x
1.15.1.1.1. Scripting Routine Tasks Using Tcl Commands 1.15.1.1.2. Traversing the Design Netlist Using Tcl Commands
1.16. Using Synopsys* Design Constraint (SDC) on RTL Files x
1.16.1. Registering the SDC-on-RTL SDC File 1.16.2. Applying the SDC-on-RTL Constraints 1.16.3. Inspecting SDC-on-RTL Constraints 1.16.4. Creating Constraints in SDC-on-RTL SDC Files 1.16.5. Using Entity-Based SDC-on-RTL Constraints 1.16.6. Types of SDC Files Used in the Quartus® Prime Software
1.16.4. Creating Constraints in SDC-on-RTL SDC Files x
1.16.4.1. Example: Using SDC-on-RTL Features
1.16.4.1. Example: Using SDC-on-RTL Features x
1.16.4.1.1. SDC-on RTL Example: Targeting Pins of Top-level Instances 1.16.4.1.2. SDC-on RTL Example: Targeting Pins in Cells 1.16.4.1.3. SDC-on RTL Example: Targeting Pins Using Wildcards 1.16.4.1.4. SDC-on RTL Example: Applying Constraints at Deeper Hierarchies
1.16.5. Using Entity-Based SDC-on-RTL Constraints x
1.16.5.1. Entity-based SDC-on-RTL Constraints Example
1.17. Using the Node Finder x
1.17.1. Node Finder Settings Reference
1.18. Synthesis Language Support x
1.18.1. Verilog and SystemVerilog Synthesis Support 1.18.2. VHDL Synthesis Support
1.18.1. Verilog and SystemVerilog Synthesis Support x
1.18.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.18.1.2. Design Libraries 1.18.1.3. Verilog HDL Configuration 1.18.1.4. Initial Constructs and Memory System Tasks 1.18.1.5. Verilog HDL Macros
1.18.1.3. Verilog HDL Configuration x
1.18.1.3.1. Hierarchical Design Configurations
1.18.2. VHDL Synthesis Support x
1.18.2.1. VHDL Input Settings (Settings Dialog Box) 1.18.2.2. VHDL Standard Libraries and Packages 1.18.2.3. VHDL wait Constructs 1.18.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.19. Synthesis Settings Reference x
1.19.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Strategies to Reduce the Overall Compilation Time 2.3. Reducing Synthesis Time 2.4. Reducing Placement Time 2.5. Reducing Routing Time 2.6. Reducing Static Timing Analysis Time 2.7. Setting Process Priority 2.8. Reducing Compilation Time Revision History
2.2. Strategies to Reduce the Overall Compilation Time x
2.2.1. Compilation on a Compute Farm 2.2.2. Enabling Multi-Processor Compilation 2.2.3. Running the ECO Compilation Flow 2.2.4. Using Block-Based Compilation
2.2.2. Enabling Multi-Processor Compilation x
2.2.2.1. Processor Base Clock Frequency 2.2.2.2. Random Access Memory (RAM) 2.2.2.3. Storage
2.3. Reducing Synthesis Time x
2.3.1. Using Precompiled Component Generation 2.3.2. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.3.3. Use Appropriate Coding Style to Reduce Synthesis Time
2.3.1. Using Precompiled Component Generation x
2.3.1.1. Enabling Precompiled Components Generation 2.3.1.2. Precompiled Component Generation Flow
2.4. Reducing Placement Time x
2.4.1. Placement Effort Multiplier Settings
2.5. Reducing Routing Time x
2.5.1. Identifying Routing Congestion 2.5.2. Changing Fitter Aggressive Routability Optimization Settings
2.5.1. Identifying Routing Congestion x
2.5.1.1. Identifying Congestion with the Global Router Congestion Hotspot Summary Report and the Global Router Wire Utilization Map 2.5.1.2. Identifying Routing Congestion with the Chip Planner
Answers to Top FAQs
1. Design Compilation
2. Reducing Compilation Time
3. Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Quartus® Prime Pro Edition User Guides

1.3.2.2. Preserving Signals for Monitoring and Debugging

The Compiler optimizes the RTL signals during synthesis and place-and-route. Unless preserved, the signal names in your RTL might not exist in the post-fit netlist after signal optimizations. For example, the compilation process can merge duplicate registers, or add tildes (~) to net names that fan-out from a node.

Preserving a signal so that it is available for debugging after synthesis and place-and-route involves the following steps:
  • Marking the signal for preservation.

    You can mark the signal directly in your RTL code or through a QSF assignment command.

  • Enabling signal preservation either for the entire project or for the instance that contains the marked signal.

    You can enable project-wide signal preservation through the Quartus® Prime GUI or a QSF assignment command. To preserve signals in an instance, use a QSF assignment command.

By separating marking signals for preservation and enabling signal preservation, you can tag signals of interest as you write your code with no effect on optimization until you enable signal preservation.

When signal preservation is enabled, the nodes marked preserve_for_debug inherit the following attributes:
Table 5.  Attributes Inherited by Nodes Marked preserve_for_debug
Attribute Result
preserve Prevents Quartus® Prime from optimizing away or retiming a register
keep Prevents Quartus® Prime from minimizing or removing a signal net during combinational logic optimization
noprune Prevents Quartus® Prime from removing or optimizing a fanout free register
dont_merge Prevents Quartus® Prime from merging a register with a duplicate register
dont_replicate Prevents Quartus® Prime from duplicating a register
Important: Instance-level signal preservation settings always override project-wide level settings. Also, signal preservation settings in your RTL always override QSF settings.
After you synthesize your design, you can locate and review your preserved signals:
  • The Preserve for Debug Assignments report shows the preservation status and name of all nodes that are marked for preservation.
  • The preserved for debug filters in Node Finder helps you quickly find preserved nodes.

The overall flow to follow to preserve signals for monitoring and debugging is as follows:

  1. Mark the signals that you want to preserve in one of the following ways:
    • Mark the signals directly in your RTL code with the preserve_for_debug attribute:
      Table 6.  Examples of Marking Signals with the preserve_for_debug Attribute in RTL
      Verilog Example VHDL Example 
      (* preserve_for_debug *) wire [3:0] counter_wire;
(* preserve_for_debug *) reg [3:0] counter_reg;

(* preserve_for_debug *) wire [15:0] decode_out_top;
(* preserve_for_debug *) reg [15:0] decode_out_reg_top;
      		 
      attribute preserve_for_debug : boolean;
attribute preserve_for_debug of counter_wire : signal is true;
attribute preserve_for_debug of counter_reg : signal is true;
attribute preserve_for_debug of decode_out : signal is true;
attribute preserve_for_debug of decode_out_reg : signal is true;
      In the Quartus® Prime GUI, you can also use the Insert Template (Edit > Insert Template) dialog box to add the preserve_for_debug attribute.
    • Mark the signals with the PRESERVE_FOR_DEBUG assignment in one of the following ways:
      • Specify the PRESERVE_FOR_DEBUG assignment for specific nodes from a command line or in your QSF file:
        set_instance_assignment -name PRESERVE_FOR_DEBUG ON -to <node hpath>
      • Specify the Preserve signal for debug assignment To any node of interest in the Assignment Editor. Select On as the assignment value.
      Important: In some rare cases, logic might be optimized away before the signal can be preserved when you use the PRESERVE_FOR_DEBUG assignment. If you encounter this issue, use the preserve_for_debug attribute in your HDL code instead.
    • Mark a system module, interface, or port for preservation in Platform Designer.

      For details, refer to "Preserving a System Module, Interface, or Port for Debugging" in Quartus® Prime Pro Edition User Guide: Platform Designer.

  2. Enable preserve for debug either project-wide or for specific instances.
    • To enable preservation and reporting project-wide, do one of the following steps:
      • Enable project-wide signal preservation from the Signal Tap Logic Analyzer settings:

        Select Assignments > Settings > Signal Tap Logic Analyzer > Enable preserve for debug assignments.

      • Specify the global PRESERVE_FOR_DEBUG_ENABLE assignment from a command line or in your QSF file:
        set_global_assignment -name PRESERVE_FOR_DEBUG_ENABLE ON
      • Specify a global Enable preserve for debug assignments assignment in the Assignment Editor. Select On as the assignment value.
      Tip: When project-wide signal preservation and reporting is enabled, use the instance-level setting to exclude instances from project-wide signal preservation and reporting.
    • To enable (or disable) preservation and reporting for only specific instances:
      • Specify the instance PRESERVE_FOR_DEBUG_ENABLE assignment as ON (or OFF) from a command line or in your QSF file:
        set_instance_assignment -name PRESERVE_FOR_DEBUG_ENABLE ON -to <instance hpath>
      • Specify the Enable preserve for debug assignments assignment To any instance of interest in the Assignment Editor. Select On (or Off) as the assignment value.
      • Specify the PRESERVE_FOR_DEBUG_ENABLE attribute with a value of ON (or OFF) on the instance in your RTL.
        Table 7.  Examples of Setting the PRESERVE_FOR_DEBUG_ENABLE Attribute in RTL
        Verilog Example VHDL Example 
        ...
(* altera_attribute = "-name PRESERVE_FOR_DEBUG_ENABLE ON" *)
decoder decoder_inst(
...
        		 
        ...
attribute altera_attribute : string;   
attribute altera_attribute of my_decoder_inst : LABEL is "-name PRESERVE_FOR_DEBUG_ENABLE ON";

...
begin
...

my_decoder_inst :  decoder
  3. Synthesize your design.

    On the Compilation Dashboard, click Analysis & Synthesis. The Compilation Report generates when synthesis is complete. You can also now use preserved for debug filters in Node Finder to help you quickly find preserved nodes.

  4. View the results of signal preservation.
    Open the Preserve for Debug Assignments report located in the Synthesis > Partition <name> > Preserve for Debug report folder.
    Figure 36. Preserve for Debug Assignments Report
  5. Run a full compilation to perform place and route of the design and Signal Tap instance by selecting Processing > Start Compilation.
    The debug signals that you preserve persist through the Fitter into the finalized compilation database.

After running a full compilation, you can debug your design with any of the Quartus® Prime debug tools.

Remember: After you have debugged your design, you might want to disable signal preservation (both globally and at the instance level) and run a full compilation to optimize signals that were preserved.
Table 8.  Debug Signal Preservation Assignments
Assignment Description Example
preserve_for_debug

(Preserve signal for debug in Assignments Editor)

Marks a signal to be preserved during compilation for post-synthesis or post-fit debugging when preserve-for-debug is enabled. set_instance_assignment -name PRESERVE_FOR_DEBUG ON -to <node hpath>
preserve_for_debug_enable

(Enable preserve for debug assignments in Assignments Editor)

Enables preserve-for-debug at either the project or instance level.

When enabled, the Compiler reports the results of signal preservation in the Preserve for Debug Assignments report after compilation.

The Compiler reports these nodes in the Preserve for Debug Assignments report following compilation. 		set_global_assignment -name PRESERVE_FOR_DEBUG_ENABLE ON

set_instance_assignment -name PRESERVE_FOR_DEBUG_ENABLE ON -to <instance hpath>

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