External Memory Interfaces Arria® 10 FPGA IP User Guide

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ID 683106
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Release Information 2. External Memory Interfaces Arria® 10 FPGA IP Introduction 3. Arria® 10 EMIF IP Product Architecture 4. Arria® 10 EMIF IP End-User Signals 5. Arria® 10 EMIF – Simulating Memory IP 6. Arria® 10 EMIF IP for DDR3 7. Arria® 10 EMIF IP for DDR4 8. Arria® 10 EMIF IP for QDR II/II+/II+ Xtreme 9. Arria® 10 EMIF IP for QDR-IV 10. Arria® 10 EMIF IP for RLDRAM 3 11. Arria® 10 EMIF IP for LPDDR3 12. Arria® 10 EMIF IP Timing Closure 13. Optimizing Controller Performance 14. Arria® 10 EMIF IP Debugging 15. External Memory Interfaces Arria® 10 FPGA IP User Guide Archives 16. Document Revision History for External Memory Interfaces Arria® 10 FPGA IP User Guide
2. External Memory Interfaces Arria® 10 FPGA IP Introduction x
2.1. Arria® 10 EMIF IP Design Flow 2.2. Arria® 10 EMIF IP Design Checklist
3. Arria® 10 EMIF IP Product Architecture x
3.1. EMIF Architecture: Introduction 3.2. Arria® 10 EMIF Sequencer 3.3. Arria® 10 EMIF Calibration 3.4. Periodic OCT Recalibration 3.5. Arria® 10 EMIF Controller 3.6. Hardware Resource Sharing Among Multiple EMIFs 3.7. Arria® 10 EMIF for Hard Processor Subsystem 3.8. Arria® 10 EMIF Ping Pong PHY 3.9. Arria® 10 EMIF and SmartVID
3.1. EMIF Architecture: Introduction x
3.1.1. I/O Subsystem 3.1.2. I/O Column 3.1.3. I/O AUX 3.1.4. I/O Bank 3.1.5. I/O Lane 3.1.6. Input DQS Clock Tree 3.1.7. PHY Clock Tree 3.1.8. PLL Reference Clock Networks 3.1.9. Clock Phase Alignment
3.1.4. I/O Bank x
3.1.4.1. Implementing a x8 Interface with Hard Memory Controller 3.1.4.2. Implementing a x72 Interface with Hard Memory Controller
3.2. Arria® 10 EMIF Sequencer x
3.2.1. DQS Tracking
3.3. Arria® 10 EMIF Calibration x
3.3.1. Calibration Stages 3.3.2. Calibration Stages Descriptions 3.3.3. Calibration Algorithms 3.3.4. Calibration Flowchart
3.4. Periodic OCT Recalibration x
3.4.1. Operation 3.4.2. Technical Restrictions 3.4.3. Efficiency Impact
3.5. Arria® 10 EMIF Controller x
3.5.1. Hard Memory Controller 3.5.2. Hard Memory Controller Rate Conversion Feature
3.5.1. Hard Memory Controller x
3.5.1.1. Hard Memory Controller Features 3.5.1.2. Hard Memory Controller Main Control Path 3.5.1.3. Data Buffer Controller
3.6. Hardware Resource Sharing Among Multiple EMIFs x
3.6.1. I/O Aux Sharing 3.6.2. I/O Bank Sharing 3.6.3. PLL Reference Clock Sharing 3.6.4. Core Clock Network Sharing
3.7. Arria® 10 EMIF for Hard Processor Subsystem x
3.7.1. Restrictions on I/O Bank Usage for Arria® 10 EMIF IP with HPS 3.7.2. Using the EMIF Debug Toolkit with Arria® 10 HPS Interfaces
3.8. Arria® 10 EMIF Ping Pong PHY x
3.8.1. Ping Pong PHY Feature Description 3.8.2. Ping Pong PHY Architecture 3.8.3. Ping Pong PHY Limitations 3.8.4. Ping Pong PHY Calibration 3.8.5. Using the Ping Pong PHY 3.8.6. Ping Pong PHY Simulation Example Design
4. Arria® 10 EMIF IP End-User Signals x
4.1. Interface and Signal Descriptions 4.2. AFI Signals 4.3. AFI 4.0 Timing Diagrams 4.4. Arria® 10 Memory Mapped Register (MMR) Tables
4.1. Interface and Signal Descriptions x
4.1.1. Intel Arria 10 EMIF IP Interfaces for DDR3 4.1.2. Intel Arria 10 EMIF IP Interfaces for DDR4 4.1.3. Intel Arria 10 EMIF IP Interfaces for LPDDR3 4.1.4. Intel Arria 10 EMIF IP Interfaces for QDR II/II+/II+ Xtreme 4.1.5. Intel Arria 10 EMIF IP Interfaces for QDR-IV 4.1.6. Intel Arria 10 EMIF IP Interfaces for RLDRAM 3
4.1.1. Intel Arria 10 EMIF IP Interfaces for DDR3 x
4.1.1.1. pll_ref_clk for DDR3 4.1.1.2. pll_locked for DDR3 4.1.1.3. pll_extra_clk_0 for DDR3 4.1.1.4. pll_extra_clk_1 for DDR3 4.1.1.5. pll_extra_clk_2 for DDR3 4.1.1.6. pll_extra_clk_3 for DDR3 4.1.1.7. oct for DDR3 4.1.1.8. mem for DDR3 4.1.1.9. status for DDR3 4.1.1.10. afi_reset_n for DDR3 4.1.1.11. afi_clk for DDR3 4.1.1.12. afi_half_clk for DDR3 4.1.1.13. afi for DDR3 4.1.1.14. emif_usr_reset_n for DDR3 4.1.1.15. emif_usr_clk for DDR3 4.1.1.16. emif_usr_reset_n_sec for DDR3 4.1.1.17. emif_usr_clk_sec for DDR3 4.1.1.18. cal_debug_reset_n for DDR3 4.1.1.19. cal_debug_clk for DDR3 4.1.1.20. cal_debug_out_reset_n for DDR3 4.1.1.21. cal_debug_out_clk for DDR3 4.1.1.22. clks_sharing_master_out for DDR3 4.1.1.23. clks_sharing_slave_in for DDR3 4.1.1.24. clks_sharing_slave_out for DDR3 4.1.1.25. ctrl_amm for DDR3 4.1.1.26. ctrl_auto_precharge for DDR3 4.1.1.27. ctrl_user_priority for DDR3 4.1.1.28. ctrl_ecc_user_interrupt for DDR3 4.1.1.29. ctrl_ecc_readdataerror for DDR3 4.1.1.30. ctrl_mmr_slave for DDR3 4.1.1.31. hps_emif for DDR3 4.1.1.32. cal_debug for DDR3 4.1.1.33. cal_debug_out for DDR3
4.1.2. Intel Arria 10 EMIF IP Interfaces for DDR4 x
4.1.2.1. pll_ref_clk for DDR4 4.1.2.2. pll_locked for DDR4 4.1.2.3. pll_extra_clk_0 for DDR4 4.1.2.4. pll_extra_clk_1 for DDR4 4.1.2.5. pll_extra_clk_2 for DDR4 4.1.2.6. pll_extra_clk_3 for DDR4 4.1.2.7. oct for DDR4 4.1.2.8. mem for DDR4 4.1.2.9. status for DDR4 4.1.2.10. afi_reset_n for DDR4 4.1.2.11. afi_clk for DDR4 4.1.2.12. afi_half_clk for DDR4 4.1.2.13. afi for DDR4 4.1.2.14. emif_usr_reset_n for DDR4 4.1.2.15. emif_usr_clk for DDR4 4.1.2.16. emif_usr_reset_n_sec for DDR4 4.1.2.17. emif_usr_clk_sec for DDR4 4.1.2.18. cal_debug_reset_n for DDR4 4.1.2.19. cal_debug_clk for DDR4 4.1.2.20. cal_debug_out_reset_n for DDR4 4.1.2.21. cal_debug_out_clk for DDR4 4.1.2.22. clks_sharing_master_out for DDR4 4.1.2.23. clks_sharing_slave_in for DDR4 4.1.2.24. clks_sharing_slave_out for DDR4 4.1.2.25. ctrl_amm for DDR4 4.1.2.26. ctrl_auto_precharge for DDR4 4.1.2.27. ctrl_user_priority for DDR4 4.1.2.28. ctrl_ecc_user_interrupt for DDR4 4.1.2.29. ctrl_ecc_readdataerror for DDR4 4.1.2.30. ctrl_mmr_slave for DDR4 4.1.2.31. hps_emif for DDR4 4.1.2.32. cal_debug for DDR4 4.1.2.33. cal_debug_out for DDR4
4.1.3. Intel Arria 10 EMIF IP Interfaces for LPDDR3 x
4.1.3.1. pll_ref_clk for LPDDR3 4.1.3.2. pll_locked for LPDDR3 4.1.3.3. pll_extra_clk_0 for LPDDR3 4.1.3.4. pll_extra_clk_1 for LPDDR3 4.1.3.5. pll_extra_clk_2 for LPDDR3 4.1.3.6. pll_extra_clk_3 for LPDDR3 4.1.3.7. oct for LPDDR3 4.1.3.8. mem for LPDDR3 4.1.3.9. status for LPDDR3 4.1.3.10. afi_reset_n for LPDDR3 4.1.3.11. afi_clk for LPDDR3 4.1.3.12. afi_half_clk for LPDDR3 4.1.3.13. afi for LPDDR3 4.1.3.14. emif_usr_reset_n for LPDDR3 4.1.3.15. emif_usr_clk for LPDDR3 4.1.3.16. cal_debug_reset_n for LPDDR3 4.1.3.17. cal_debug_clk for LPDDR3 4.1.3.18. cal_debug_out_reset_n for LPDDR3 4.1.3.19. cal_debug_out_clk for LPDDR3 4.1.3.20. clks_sharing_master_out for LPDDR3 4.1.3.21. clks_sharing_slave_in for LPDDR3 4.1.3.22. clks_sharing_slave_out for LPDDR3 4.1.3.23. ctrl_user_priority for LPDDR3 4.1.3.24. ctrl_mmr_slave for LPDDR3 4.1.3.25. cal_debug for LPDDR3 4.1.3.26. cal_debug_out for LPDDR3
4.1.4. Intel Arria 10 EMIF IP Interfaces for QDR II/II+/II+ Xtreme x
4.1.4.1. pll_ref_clk for QDR II/II+/II+ Xtreme 4.1.4.2. pll_locked for QDR II/II+/II+ Xtreme 4.1.4.3. pll_extra_clk_0 for QDR II/II+/II+ Xtreme 4.1.4.4. pll_extra_clk_1 for QDR II/II+/II+ Xtreme 4.1.4.5. pll_extra_clk_2 for QDR II/II+/II+ Xtreme 4.1.4.6. pll_extra_clk_3 for QDR II/II+/II+ Xtreme 4.1.4.7. oct for QDR II/II+/II+ Xtreme 4.1.4.8. mem for QDR II/II+/II+ Xtreme 4.1.4.9. status for QDR II/II+/II+ Xtreme 4.1.4.10. emif_usr_reset_n for QDR II/II+/II+ Xtreme 4.1.4.11. emif_usr_clk for QDR II/II+/II+ Xtreme 4.1.4.12. cal_debug_reset_n for QDR II/II+/II+ Xtreme 4.1.4.13. cal_debug_clk for QDR II/II+/II+ Xtreme 4.1.4.14. cal_debug_out_reset_n for QDR II/II+/II+ Xtreme 4.1.4.15. cal_debug_out_clk for QDR II/II+/II+ Xtreme 4.1.4.16. clks_sharing_master_out for QDR II/II+/II+ Xtreme 4.1.4.17. clks_sharing_slave_in for QDR II/II+/II+ Xtreme 4.1.4.18. clks_sharing_slave_out for QDR II/II+/II+ Xtreme 4.1.4.19. ctrl_amm for QDR II/II+/II+ Xtreme 4.1.4.20. cal_debug for QDR II/II+/II+ Xtreme 4.1.4.21. cal_debug_out for QDR II/II+/II+ Xtreme
4.1.5. Intel Arria 10 EMIF IP Interfaces for QDR-IV x
4.1.5.1. pll_ref_clk for QDR-IV 4.1.5.2. pll_locked for QDR-IV 4.1.5.3. pll_extra_clk_0 for QDR-IV 4.1.5.4. pll_extra_clk_1 for QDR-IV 4.1.5.5. pll_extra_clk_2 for QDR-IV 4.1.5.6. pll_extra_clk_3 for QDR-IV 4.1.5.7. oct for QDR-IV 4.1.5.8. mem for QDR-IV 4.1.5.9. status for QDR-IV 4.1.5.10. afi_reset_n for QDR-IV 4.1.5.11. afi_clk for QDR-IV 4.1.5.12. afi_half_clk for QDR-IV 4.1.5.13. afi for QDR-IV 4.1.5.14. emif_usr_reset_n for QDR-IV 4.1.5.15. emif_usr_clk for QDR-IV 4.1.5.16. cal_debug_reset_n for QDR-IV 4.1.5.17. cal_debug_clk for QDR-IV 4.1.5.18. cal_debug_out_reset_n for QDR-IV 4.1.5.19. cal_debug_out_clk for QDR-IV 4.1.5.20. clks_sharing_master_out for QDR-IV 4.1.5.21. clks_sharing_slave_in for QDR-IV 4.1.5.22. clks_sharing_slave_out for QDR-IV 4.1.5.23. ctrl_amm for QDR-IV 4.1.5.24. cal_debug for QDR-IV 4.1.5.25. cal_debug_out for QDR-IV
4.1.6. Intel Arria 10 EMIF IP Interfaces for RLDRAM 3 x
4.1.6.1. pll_ref_clk for RLDRAM 3 4.1.6.2. pll_locked for RLDRAM 3 4.1.6.3. pll_extra_clk_0 for RLDRAM 3 4.1.6.4. pll_extra_clk_1 for RLDRAM 3 4.1.6.5. pll_extra_clk_2 for RLDRAM 3 4.1.6.6. pll_extra_clk_3 for RLDRAM 3 4.1.6.7. oct for RLDRAM 3 4.1.6.8. mem for RLDRAM 3 4.1.6.9. status for RLDRAM 3 4.1.6.10. afi_reset_n for RLDRAM 3 4.1.6.11. afi_clk for RLDRAM 3 4.1.6.12. afi_half_clk for RLDRAM 3 4.1.6.13. afi for RLDRAM 3 4.1.6.14. cal_debug_reset_n for RLDRAM 3 4.1.6.15. cal_debug_clk for RLDRAM 3 4.1.6.16. cal_debug_out_reset_n for RLDRAM 3 4.1.6.17. cal_debug_out_clk for RLDRAM 3 4.1.6.18. clks_sharing_master_out for RLDRAM 3 4.1.6.19. clks_sharing_slave_in for RLDRAM 3 4.1.6.20. clks_sharing_slave_out for RLDRAM 3 4.1.6.21. cal_debug for RLDRAM 3 4.1.6.22. cal_debug_out for RLDRAM 3
4.2. AFI Signals x
4.2.1. AFI Clock and Reset Signals 4.2.2. AFI Address and Command Signals 4.2.3. AFI Write Data Signals 4.2.4. AFI Read Data Signals 4.2.5. AFI Calibration Status Signals 4.2.6. AFI Tracking Management Signals 4.2.7. AFI Shadow Register Management Signals
4.3. AFI 4.0 Timing Diagrams x
4.3.1. AFI Address and Command Timing Diagrams 4.3.2. AFI Write Sequence Timing Diagrams 4.3.3. AFI Read Sequence Timing Diagrams 4.3.4. AFI Calibration Status Timing Diagram
4.4. Arria® 10 Memory Mapped Register (MMR) Tables x
4.4.1. ctrlcfg0 4.4.2. ctrlcfg1 4.4.3. dramtiming0 4.4.4. sbcfg1 4.4.5. caltiming0 4.4.6. caltiming1 4.4.7. caltiming2 4.4.8. caltiming3 4.4.9. caltiming4 4.4.10. caltiming9 4.4.11. dramaddrw 4.4.12. sideband0 4.4.13. sideband1 4.4.14. sideband2 4.4.15. sideband3 4.4.16. sideband4 4.4.17. sideband5 4.4.18. sideband6 4.4.19. sideband7 4.4.20. sideband8 4.4.21. sideband9 4.4.22. sideband10 4.4.23. sideband11 4.4.24. sideband12 4.4.25. sideband13 4.4.26. dramsts 4.4.27. niosreserve0 4.4.28. niosreserve1 4.4.29. ecc3: ECC Error and Interrupt Configuration 4.4.30. ecc4: Status and Error Information 4.4.31. ecc5: Address of Most Recent SBE/DBE 4.4.32. ecc6: Address of Most Recent Correction Command Dropped
5. Arria® 10 EMIF – Simulating Memory IP x
5.1. Simulation Options 5.2. Simulation Walkthrough
5.2. Simulation Walkthrough x
5.2.1. Calibration Modes 5.2.2. Abstract PHY Simulation 5.2.3. Simulation Scripts 5.2.4. Functional Simulation with Verilog HDL 5.2.5. Functional Simulation with VHDL 5.2.6. Simulating the Design Example
6. Arria® 10 EMIF IP for DDR3 x
6.1. Parameter Descriptions 6.2. Board Skew Equations 6.3. Pin and Resource Planning 6.4. DDR3 Board Design Guidelines
6.1. Parameter Descriptions x
6.1.1. Intel Arria 10 EMIF IP DDR3 Parameters: General 6.1.2. Intel Arria 10 EMIF IP DDR3 Parameters: Memory 6.1.3. Intel Arria 10 EMIF IP DDR3 Parameters: Mem I/O 6.1.4. Intel Arria 10 EMIF IP DDR3 Parameters: FPGA I/O 6.1.5. Intel Arria 10 EMIF IP DDR3 Parameters: Mem Timing 6.1.6. Intel Arria 10 EMIF IP DDR3 Parameters: Board 6.1.7. Intel Arria 10 EMIF IP DDR3 Parameters: Controller 6.1.8. Intel Arria 10 EMIF IP DDR3 Parameters: Diagnostics 6.1.9. Intel Arria 10 EMIF IP DDR3 Parameters: Example Designs
6.2. Board Skew Equations x
6.2.1. Equations for DDR3 Board Skew Parameters
6.3. Pin and Resource Planning x
6.3.1. Interface Pins 6.3.2. FPGA Resources 6.3.3. Pin Guidelines for Arria® 10 EMIF IP
6.3.1. Interface Pins x
6.3.1.1. Estimating Pin Requirements 6.3.1.2. DIMM Options 6.3.1.3. Maximum Number of Interfaces
6.3.2. FPGA Resources x
6.3.2.1. OCT 6.3.2.2. PLL
6.3.3. Pin Guidelines for Arria® 10 EMIF IP x
6.3.3.1. General Guidelines 6.3.3.2. x4 DIMM Implementation 6.3.3.3. Command and Address Signals 6.3.3.4. Clock Signals 6.3.3.5. Data, Data Strobes, DM/DBI, and Optional ECC Signals 6.3.3.6. Resource Sharing Guidelines (Multiple Interfaces) 6.3.3.7. Ping-Pong PHY Implementation
6.4. DDR3 Board Design Guidelines x
6.4.1. Terminations and Slew Rates with Arria® 10 Devices 6.4.2. Channel Signal Integrity Measurement 6.4.3. Layout Approach 6.4.4. Design Layout Guidelines 6.4.5. Package Deskew
6.4.1. Terminations and Slew Rates with Arria® 10 Devices x
6.4.1.1. Dynamic On-Chip Termination (OCT) in Arria® 10 Devices 6.4.1.2. Choosing Terminations on Arria® 10 Devices 6.4.1.3. On-Chip Termination Recommendations for Arria® 10 Devices 6.4.1.4. Slew Rates
6.4.2. Channel Signal Integrity Measurement x
6.4.2.1. Importance of Accurate Channel Signal Integrity Information 6.4.2.2. Understanding Channel Signal Integrity Measurement 6.4.2.3. How to Enter Calculated Channel Signal Integrity Values 6.4.2.4. Guidelines for Calculating DDR3 Channel Signal Integrity
6.4.4. Design Layout Guidelines x
6.4.4.1. General Layout Guidelines 6.4.4.2. Layout Guidelines 6.4.4.3. Length Matching Rules 6.4.4.4. Spacing Guidelines 6.4.4.5. Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits) 6.4.4.6. Fly-By Network Design for Clock, Command, and Address Signals
6.4.5. Package Deskew x
6.4.5.1. DQ/DQS/DM Deskew 6.4.5.2. Address and Command Deskew 6.4.5.3. Package Deskew Recommendations for Arria® 10 Devices 6.4.5.4. Deskew Example 6.4.5.5. Package Migration
7. Arria® 10 EMIF IP for DDR4 x
7.1. Parameter Descriptions 7.2. Board Skew Equations 7.3. Pin and Resource Planning 7.4. DDR4 Board Design Guidelines
7.1. Parameter Descriptions x
7.1.1. Intel Arria 10 EMIF IP DDR4 Parameters: General 7.1.2. Intel Arria 10 EMIF IP DDR4 Parameters: Memory 7.1.3. Intel Arria 10 EMIF IP DDR4 Parameters: Mem I/O 7.1.4. Intel Arria 10 EMIF IP DDR4 Parameters: FPGA I/O 7.1.5. Intel Arria 10 EMIF IP DDR4 Parameters: Mem Timing 7.1.6. Intel Arria 10 EMIF IP DDR4 Parameters: Board 7.1.7. Intel Arria 10 EMIF IP DDR4 Parameters: Controller 7.1.8. Intel Arria 10 EMIF IP DDR4 Parameters: Diagnostics 7.1.9. Intel Arria 10 EMIF IP DDR4 Parameters: Example Designs
7.2. Board Skew Equations x
7.2.1. Equations for DDR4 Board Skew Parameters
7.3. Pin and Resource Planning x
7.3.1. Interface Pins 7.3.2. FPGA Resources 7.3.3. Pin Guidelines for Arria® 10 EMIF IP 7.3.4. Resource Sharing Guidelines (Multiple Interfaces)
7.3.1. Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. DIMM Options 7.3.1.3. Maximum Number of Interfaces
7.3.2. FPGA Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Arria® 10 EMIF IP x
7.3.3.1. General Guidelines Multiple Interfaces in the Same I/O Column I/O Banks Selection Address/Command Pins Location CK Pins Assignment PLL Reference Clock Pin Placement RZQ Pin Placement DQ and DQS Pins Assignment Sharing an I/O Bank Across Multiple Interfaces 7.3.3.2. x4 DIMM Implementation 7.3.3.3. Command and Address Signals 7.3.3.4. Clock Signals 7.3.3.5. Data, Data Strobes, DM/DBI, and Optional ECC Signals 7.3.3.6. alert_n Pin Termination Recommendation
7.4. DDR4 Board Design Guidelines x
7.4.1. Terminations and Slew Rates with Arria® 10 Devices 7.4.2. Channel Signal Integrity Measurement 7.4.3. Layout Approach 7.4.4. Design Layout Guidelines 7.4.5. Package Deskew
7.4.1. Terminations and Slew Rates with Arria® 10 Devices x
7.4.1.1. Dynamic On-Chip Termination (OCT) in Arria® 10 Devices 7.4.1.2. Dynamic On-Die Termination (ODT) in DDR4 7.4.1.3. Choosing Terminations on Arria® 10 Devices 7.4.1.4. On-Chip Termination Recommendations for Arria® 10 Devices 7.4.1.5. Slew Rates
7.4.2. Channel Signal Integrity Measurement x
7.4.2.1. Importance of Accurate Channel Signal Integrity Information 7.4.2.2. Understanding Channel Signal Integrity Measurement 7.4.2.3. How to Enter Calculated Channel Signal Integrity Values 7.4.2.4. Guidelines for Calculating DDR4 Channel Signal Integrity
7.4.4. Design Layout Guidelines x
7.4.4.1. General Layout Guidelines 7.4.4.2. Layout Guidelines 7.4.4.3. Length Matching Rules 7.4.4.4. Spacing Guidelines 7.4.4.5. Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits) 7.4.4.6. Fly-By Network Design for Clock, Command, and Address Signals 7.4.4.7. Additional Layout Guidelines for DDR4 Twin-die Devices
7.4.5. Package Deskew x
7.4.5.1. DQ/DQS/DM Deskew 7.4.5.2. Address and Command Deskew 7.4.5.3. Package Deskew Recommendations for Arria® 10 Devices 7.4.5.4. Deskew Example 7.4.5.5. Package Migration
8. Arria® 10 EMIF IP for QDR II/II+/II+ Xtreme x
8.1. Parameter Descriptions 8.2. Board Skew Equations 8.3. Pin and Resource Planning 8.4. QDR II/II+/II+ Xtreme Board Design Guidelines
8.1. Parameter Descriptions x
8.1.1. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: General 8.1.2. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Memory 8.1.3. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: FPGA I/O 8.1.4. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem Timing 8.1.5. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Board 8.1.6. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Controller 8.1.7. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Diagnostics 8.1.8. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Example Designs
8.2. Board Skew Equations x
8.2.1. Equations for QDRII, QDRII+, and QDRII+ Xtreme Board Skew Parameters
8.3. Pin and Resource Planning x
8.3.1. Interface Pins
8.3.1. Interface Pins x
8.3.1.1. Estimating Pin Requirements 8.3.1.2. Maximum Number of Interfaces 8.3.1.3. FPGA Resources 8.3.1.4. OCT 8.3.1.5. PLL 8.3.1.6. Pin Guidelines for Arria® 10 EMIF IP
8.3.1.6. Pin Guidelines for Arria® 10 EMIF IP x
8.3.1.6.1. General Guidelines 8.3.1.6.2. QDR II, QDR II+ and QDR II+ Xtreme SRAM Command Signals 8.3.1.6.3. QDR II, QDR II+ and QDR II+ Xtreme SRAM Address Signals 8.3.1.6.4. QDR II, QDR II+, and QDR II+ Xtreme SRAM Clock Signals 8.3.1.6.5. QDR II, QDR II+ and QDR II+ Xtreme SRAM Data, BWS, and QVLD Signals 8.3.1.6.6. Resource Sharing Guidelines (Multiple Interfaces)
8.4. QDR II/II+/II+ Xtreme Board Design Guidelines x
8.4.1. QDR II SRAM Configurations 8.4.2. General Layout Guidelines 8.4.3. QDR II Layout Guidelines 8.4.4. QDR II SRAM Layout Approach 8.4.5. Package Deskew 8.4.6. Package Migration 8.4.7. Slew Rates
9. Arria® 10 EMIF IP for QDR-IV x
9.1. Parameter Descriptions 9.2. Board Skew Equations 9.3. Pin and Resource Planning 9.4. QDR-IV Board Design Guidelines
9.1. Parameter Descriptions x
9.1.1. Intel Arria 10 EMIF IP QDR-IV Parameters: General 9.1.2. Intel Arria 10 EMIF IP QDR-IV Parameters: Memory 9.1.3. Intel Arria 10 EMIF IP QDR-IV Parameters: FPGA I/O 9.1.4. Intel Arria 10 EMIF IP QDR-IV Parameters: Mem Timing 9.1.5. Intel Arria 10 EMIF IP QDR-IV Parameters: Board 9.1.6. Intel Arria 10 EMIF IP QDR-IV Parameters: Controller 9.1.7. Intel Arria 10 EMIF IP QDR-IV Parameters: Diagnostics 9.1.8. Intel Arria 10 EMIF IP QDR-IV Parameters: Example Designs
9.2. Board Skew Equations x
9.2.1. Equations for QDR-IV Board Skew Parameters
9.3. Pin and Resource Planning x
9.3.1. Interface Pins
9.3.1. Interface Pins x
9.3.1.1. Estimating Pin Requirements 9.3.1.2. Maximum Number of Interfaces 9.3.1.3. FPGA Resources 9.3.1.4. OCT 9.3.1.5. PLL 9.3.1.6. Pin Guidelines for Arria® 10 EMIF IP 9.3.1.7. Resource Sharing Guidelines (Multiple Interfaces)
9.3.1.6. Pin Guidelines for Arria® 10 EMIF IP x
9.3.1.6.1. General Guidelines 9.3.1.6.2. QDR IV SRAM Commands and Addresses, AP, and AINV Signals 9.3.1.6.3. QDR IV SRAM Clock Signals 9.3.1.6.4. QDR IV SRAM Data, DINV, and QVLD Signals
9.4. QDR-IV Board Design Guidelines x
9.4.1. QDR-IV Layout Approach 9.4.2. General Layout Guidelines 9.4.3. QDR-IV Layout Guidelines 9.4.4. Package Deskew 9.4.5. Package Migration 9.4.6. Slew Rates
10. Arria® 10 EMIF IP for RLDRAM 3 x
10.1. Parameter Descriptions 10.2. Board Skew Equations 10.3. Pin and Resource Planning 10.4. RLDRAM 3 Board Design Guidelines
10.1. Parameter Descriptions x
10.1.1. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: General 10.1.2. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Memory 10.1.3. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: FPGA I/O 10.1.4. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Mem Timing 10.1.5. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Board 10.1.6. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Controller 10.1.7. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Diagnostics 10.1.8. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Example Designs
10.2. Board Skew Equations x
10.2.1. Equations for RLDRAM 3 Board Skew Parameters
10.3. Pin and Resource Planning x
10.3.1. Interface Pins
10.3.1. Interface Pins x
10.3.1.1. Estimating Pin Requirements 10.3.1.2. Maximum Number of Interfaces 10.3.1.3. FPGA Resources 10.3.1.4. OCT 10.3.1.5. PLL 10.3.1.6. Pin Guidelines for Arria® 10 EMIF IP 10.3.1.7. Resource Sharing Guidelines (Multiple Interfaces)
10.3.1.6. Pin Guidelines for Arria® 10 EMIF IP x
10.3.1.6.1. General Guidelines 10.3.1.6.2. RLDRAM 3 Commands and Addresses 10.3.1.6.3. RLDRAM 3 Clock Signals 10.3.1.6.4. RLDRAM 3 Data, DM and QVLD Signals
10.4. RLDRAM 3 Board Design Guidelines x
10.4.1. RLDRAM 3 Configurations 10.4.2. General Layout Guidelines 10.4.3. RLDRAM 3 Layout Guidelines 10.4.4. Layout Approach 10.4.5. Package Deskew 10.4.6. Package Migration
11. Arria® 10 EMIF IP for LPDDR3 x
11.1. Parameter Descriptions 11.2. Board Skew Equations 11.3. Pin and Resource Planning 11.4. LPDDR3 Board Design Guidelines
11.1. Parameter Descriptions x
11.1.1. Intel Arria 10 EMIF IP LPDDR3 Parameters: General 11.1.2. Intel Arria 10 EMIF IP LPDDR3 Parameters: Memory 11.1.3. Intel Arria 10 EMIF IP LPDDR3 Parameters: Mem I/O 11.1.4. Intel Arria 10 EMIF IP LPDDR3 Parameters: FPGA I/O 11.1.5. Intel Arria 10 EMIF IP LPDDR3 Parameters: Mem Timing 11.1.6. Intel Arria 10 EMIF IP LPDDR3 Parameters: Board 11.1.7. Intel Arria 10 EMIF IP LPDDR3 Parameters: Controller 11.1.8. Intel Arria 10 EMIF IP LPDDR3 Parameters: Diagnostics 11.1.9. Intel Arria 10 EMIF IP LPDDR3 Parameters: Example Designs
11.2. Board Skew Equations x
11.2.1. Equations for LPDDR3 Board Skew Parameters
11.3. Pin and Resource Planning x
11.3.1. Interface Pins
11.3.1. Interface Pins x
11.3.1.1. Estimating Pin Requirements 11.3.1.2. Maximum Number of Interfaces 11.3.1.3. FPGA Resources 11.3.1.4. OCT 11.3.1.5. PLL 11.3.1.6. Pin Guidelines for Arria® 10 EMIF IP
11.3.1.6. Pin Guidelines for Arria® 10 EMIF IP x
11.3.1.6.1. General Guidelines 11.3.1.6.2. LPDDR3 Clock Signal 11.3.1.6.3. LPDDR3 Command and Address Signal 11.3.1.6.4. LPDDR3 Data, Data Strobe, and DM Signals 11.3.1.6.5. Resource Sharing Guidelines (Multiple Interfaces)
11.4. LPDDR3 Board Design Guidelines x
11.4.1. Terminations and Slew Rates with Arria® 10 Devices 11.4.2. Channel Signal Integrity Measurement 11.4.3. Layout Approach 11.4.4. Design Layout Guidelines 11.4.5. Package Deskew
11.4.1. Terminations and Slew Rates with Arria® 10 Devices x
11.4.1.1. Dynamic On-Chip Termination (OCT) in Arria® 10 Devices 11.4.1.2. Choosing Terminations on Arria® 10 Devices 11.4.1.3. On-Chip Termination Recommendations for Arria® 10 Devices
11.4.2. Channel Signal Integrity Measurement x
11.4.2.1. Importance of Accurate Channel Signal Integrity Information 11.4.2.2. Understanding Channel Signal Integrity Measurement 11.4.2.3. How to Enter Calculated Channel Signal Integrity Values 11.4.2.4. Guidelines for Calculating DDR3 Channel Signal Integrity
11.4.4. Design Layout Guidelines x
11.4.4.1. General Layout Guidelines 11.4.4.2. Layout Guidelines 11.4.4.3. Length Matching Rules 11.4.4.4. Spacing Guidelines 11.4.4.5. Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits) 11.4.4.6. Fly-By Network Design for Clock, Command, and Address Signals
11.4.5. Package Deskew x
11.4.5.1. DQ/DQS/DM Deskew 11.4.5.2. Address and Command Deskew 11.4.5.3. Package Deskew Recommendations for Arria® 10 Devices 11.4.5.4. Deskew Example 11.4.5.5. Package Migration
12. Arria® 10 EMIF IP Timing Closure x
12.1. Timing Closure 12.2. Timing Report DDR 12.3. Optimizing Timing 12.4. Early I/O Timing Estimation
12.1. Timing Closure x
12.1.1. Timing Analysis
12.1.1. Timing Analysis x
12.1.1.1. PHY or Core 12.1.1.2. I/O Timing
12.1.1.2. I/O Timing x
12.1.1.2.1. Read Capture 12.1.1.2.2. Write 12.1.1.2.3. Address and Command 12.1.1.2.4. DQS Gating / Postamble 12.1.1.2.5. Write Leveling
12.4. Early I/O Timing Estimation x
12.4.1. Performing Early I/O Timing Analysis
13. Optimizing Controller Performance x
13.1. Interface Standard 13.2. Bank Management Efficiency 13.3. Data Transfer 13.4. Improving Controller Efficiency
13.4. Improving Controller Efficiency x
13.4.1. Auto-Precharge Commands 13.4.2. Latency 13.4.3. Calibration 13.4.4. Bank Interleaving 13.4.5. Additive Latency and Bank Interleaving 13.4.6. User-Controlled Refresh 13.4.7. Frequency of Operation 13.4.8. Series of Reads or Writes 13.4.9. Data Reordering 13.4.10. Starvation Control 13.4.11. Command Reordering 13.4.12. Bandwidth 13.4.13. Enable Command Priority Control
13.4.2. Latency x
13.4.2.1. Additive Latency
13.4.6. User-Controlled Refresh x
13.4.6.1. Back-to-Back User-Controlled Refresh Usage
14. Arria® 10 EMIF IP Debugging x
14.1. Interface Configuration Performance Issues 14.2. Functional Issue Evaluation 14.3. Timing Issue Characteristics 14.4. Verifying Memory IP Using the Signal Tap II Logic Analyzer 14.5. Hardware Debugging Guidelines 14.6. Categorizing Hardware Issues 14.7. Debugging Arria® 10 EMIF IP 14.8. Using the Traffic Generator with the Generated Design Example
14.1. Interface Configuration Performance Issues x
14.1.1. Interface Configuration Bottleneck and Efficiency Issues
14.2. Functional Issue Evaluation x
14.2.1. Intel® IP Memory Model 14.2.2. Vendor Memory Model 14.2.3. Transcript Window Messages 14.2.4. Modifying the Example Driver to Replicate the Failure
14.3. Timing Issue Characteristics x
14.3.1. Evaluating FPGA Timing Issues 14.3.2. Evaluating External Memory Interface Timing Issues
14.4. Verifying Memory IP Using the Signal Tap II Logic Analyzer x
14.4.1. Signals to Monitor with the Signal Tap II Logic Analyzer
14.5. Hardware Debugging Guidelines x
14.5.1. Create a Simplified Design that Demonstrates the Same Issue 14.5.2. Measure Power Distribution Network 14.5.3. Measure Signal Integrity and Setup and Hold Margin 14.5.4. Vary Voltage 14.5.5. Operate at a Lower Speed 14.5.6. Determine Whether the Issue Exists in Previous Versions of Software 14.5.7. Determine Whether the Issue Exists in the Current Version of Software 14.5.8. Try A Different PCB 14.5.9. Try Other Configurations 14.5.10. Debugging Checklist
14.6. Categorizing Hardware Issues x
14.6.1. Signal Integrity Issues 14.6.2. Hardware and Calibration Issues
14.6.1. Signal Integrity Issues x
14.6.1.1. Characteristics of Signal Integrity Issues 14.6.1.2. Evaluating SignaI Integrity Issues
14.6.1.2. Evaluating SignaI Integrity Issues x
14.6.1.2.1. Skew 14.6.1.2.2. Crosstalk 14.6.1.2.3. Power System 14.6.1.2.4. Clock Signals 14.6.1.2.5. Read Data Valid Window and Eye Diagram 14.6.1.2.6. Write Data Valid Window and Eye Diagram 14.6.1.2.7. OCT and ODT Usage
14.6.2. Hardware and Calibration Issues x
14.6.2.1. Postamble Timing Issues and Margin 14.6.2.2. Intermittent Issue Evaluation
14.7. Debugging Arria® 10 EMIF IP x
14.7.1. Debugging With the External Memory Interface Debug Toolkit 14.7.2. On-Chip Debug Port for Arria® 10 EMIF IP 14.7.3. Efficiency Monitor and Protocol Checker
14.7.1. Debugging With the External Memory Interface Debug Toolkit x
14.7.1.1. User Interface 14.7.1.2. Communication 14.7.1.3. Setup and Use 14.7.1.4. Configuring Your EMIF IP for Use with the Debug Toolkit 14.7.1.5. Reports 14.7.1.6. On-Die Termination Calibration 14.7.1.7. Eye Diagram 14.7.1.8. Driver Margining for Arria® 10 EMIF IP 14.7.1.9. Example Tcl Script for Running the EMIF Debug Toolkit 14.7.1.10. Using the EMIF Debug Toolkit with Arria® 10 HPS Interfaces
14.7.1.4. Configuring Your EMIF IP for Use with the Debug Toolkit x
14.7.1.4.1. Daisy-Chaining Additional EMIF IP Cores for Debugging 14.7.1.4.2. General Workflow 14.7.1.4.3. Linking the Project to a Device 14.7.1.4.4. Establishing Communication to Connections 14.7.1.4.5. Selecting an Active Interface
14.7.1.8. Driver Margining for Arria® 10 EMIF IP x
14.7.1.8.1. Determining Margin
14.7.2. On-Chip Debug Port for Arria® 10 EMIF IP x
14.7.2.1. EMIF On-Chip Debug Port 14.7.2.2. Access Protocol
14.7.3. Efficiency Monitor and Protocol Checker x
14.7.3.1. Including the Efficiency Monitor and Protocol Checker in Your Generated IP 14.7.3.2. Running the Efficiency Monitor with the External Memory Debug Toolkit 14.7.3.3. Communicating Directly to the Efficiency Monitor and Protocol Checker
1. Release Information
2. External Memory Interfaces Arria® 10 FPGA IP Introduction
3. Arria® 10 EMIF IP Product Architecture
4. Arria® 10 EMIF IP End-User Signals
5. Arria® 10 EMIF – Simulating Memory IP
6. Arria® 10 EMIF IP for DDR3
7. Arria® 10 EMIF IP for DDR4
8. Arria® 10 EMIF IP for QDR II/II+/II+ Xtreme
9. Arria® 10 EMIF IP for QDR-IV
10. Arria® 10 EMIF IP for RLDRAM 3
11. Arria® 10 EMIF IP for LPDDR3
12. Arria® 10 EMIF IP Timing Closure
13. Optimizing Controller Performance
14. Arria® 10 EMIF IP Debugging
15. External Memory Interfaces Arria® 10 FPGA IP User Guide Archives
16. Document Revision History for External Memory Interfaces Arria® 10 FPGA IP User Guide

7.3.3.1. General Guidelines

You should follow the recommended guidelines when performing pin placement for all external memory interface pins targeting Arria® 10 devices, whether you are using the hard memory controller or your own solution.

If you are using the hard memory controller, you should employ the relative pin locations defined in the <variation_name>/altera_emif_arch_nf_version number/<synth|sim>/<variation_name>_altera_emif_arch_nf_version number_<unique ID>_readme.txt file, which is generated with your IP.

Note:
  1. The number of I/O pins in an I/O bank and the availability of I/O banks varies across device packages. Each memory interface requires at least one I/O bank with 48 I/O pins for the address and command pins. I/O banks with less than 48 I/O pins can support data pins only. For details about the I/O banks available for each device package and the locations of consecutive I/O banks, refer to Memory Interfaces Support in Intel Arria 10 Device Packages and related links, in the Arria® 10 Core Fabric and General Purpose I/Os Handbook.
  2. EMIF IP pin-out requirements for the Arria® 10 Hard Processor Subsystem (HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IP defines a fixed pin-out in the Quartus® Prime IP file (.qip), based on the IP configuration. When targeting Arria® 10 HPS, you do not need to make location assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the Quartus® Prime software. Alternatively, consult the device handbook or the device pin-out files. For information on how you can customize the HPS EMIF pin-out, refer to Restrictions on I/O Bank Usage for Arria® 10 EMIF IP with HPS.
  3. Ping Pong PHY, PHY only, RLDRAMx , QDRx and LPDDR3 are not supported with HPS.

Observe the following general guidelines when placing pins for your Arria® 10 external memory interface:

  1. Ensure that the pins of a single external memory interface reside within a single I/O column.
  2. An external memory interface can occupy one or more banks in the same I/O column. When an interface must occupy multiple banks, ensure that those banks are adjacent to one another.
  3. Any pin in the same bank that is not used by an external memory interface is available for use as a general purpose I/O of compatible voltage and termination settings.
  4. All address and command pins and their associated clock pins (CK and CK#) must reside within a single bank. The bank containing the address and command pins is identified as the address and command bank.
  5. To minimize latency, when the interface uses more than two banks, you must select the center bank of the interface as the address and command bank.
  6. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the Arria® 10 External Memory Interface Pin Information File, which is available on www.altera.com.

    You do not have to place every address and command pin manually. If you assign the location for one address and command pin, the Fitter automatically places the remaining address and command pins.

    Note: The pin-out scheme is a hardware requirement that you must follow, and can vary according to the topology of the memory device. Some schemes require three lanes to implement address and command pins, while others require four lanes. To determine which scheme to follow, refer to the messages window during parameterization of your IP, or to the <variation_name>/altera_emif_arch_nf_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nf_<version>_<unique ID>_readme.txt file after you have generated your IP.
  7. An unused I/O lane in the address and command bank can serve to implement a data group, such as a x8 DQS group. The data group must be from the same controller as the address and command signals.
  8. An I/O lane must not be used by both address and command pins and data pins.
  9. Place read data groups according to the DQS grouping in the pin table and Pin Planner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQ and CQ# / QK and QK#) must reside at physical pins capable of functioning as DQS/CQ and DQSn/CQn for a specific read data group size. You must place the associated read data pins (such as DQ and Q), within the same group.
    Note:
    1. Unlike other device families, there is no need to swap CQ/CQ# pins in certain QDR II and QDR II+ latency configurations.
    2. QDR-IV requires that the polarity of all QKB/QKB# pins be swapped with respect to the polarity of the differential buffer inputs on the FPGA to ensure correct data capture on port B. All QKB pins on the memory device must be connected to the negative pins of the input buffers on the FPGA side, and all QKB# pins on the memory device must be connected to the positive pins of the input buffers on the FPGA side. Notice that the port names at the top-level of the IP already reflect this swap (that is, mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive buffer leg).
  10. You can implement two x4 DQS groups with a single I/O lane. The pin table specifies which pins within an I/O lane can be used for the two pairs of DQS and DQS# signals. In addition, for x4 DQS groups you must observe the following rules:
    • There must be an even number of x4 groups in an external memory interface.
    • DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly, DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS group X and DQS group X+1 must be in the same I/O lane, where X is an even number.
    • When placing DQ pins in x4 mode, it is important to stay within an I/O lane when swapping pin locations. In other words, you may swap DQ pins within a given DQS group or across an adjacent DQS group, so long as you are within the same I/O lane. The following table illustrates an example, where DATA_A and DATA_B are swap groups, meaning that any pin in that index can move within that range of pins.
      Index Within Lane DQS x4 Locations
      11 DATA_B[3:0]
      10 DATA_B[3:0]
      9 DQS_Bn
      8 DQS_Bp
      7 DATA_B[3:0]
      6 DATA_B[3:0]
      5 DQS_An
      4 DQS_Ap
      3 DATA_A[3:0]
      2 DATA_A[3:0]
      1 DATA_A[3:0]
      0 DATA_A[3:0]
  11. You should place the write data groups according to the DQS grouping in the pin table and Pin Planner. Output-only data clocks for QDR II, QDR II+, and QDR II+ Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, but must be placed on a differential pin pair. They must be placed in the same I/O bank as the corresponding DQS group.
    Note: For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.
  12. For protocols and topologies with bidirectional data pins where a write data group consists of multiple read data groups, you should place the data groups and their respective write and read clock in the same bank to improve I/O timing.

    You do not need to specify the location of every data pin manually. If you assign the location for the read capture strobe/clock pin pairs, the Fitter will automatically place the remaining data pins.

  13. Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/O pin and another in the pairing pin for that I/O pin. It is recommended—though not required—that you follow the same rule for DBI pins, so that at a later date you have the freedom to repurpose the pin as DM.
Note:
  1. x4 mode does not support DM/DBI, or Arria® 10 EMIF IP for HPS.
  2. If you are using an Arria® 10 EMIF IP-based RLDRAM II or RLDRAM 3 external memory interface, you should ensure that all the pins in a DQS group (that is, DQ, DM, DK, and QK) are placed in the same I/O bank. This requirement facilitates timing closure and is necessary for successful compilation of your design.

Multiple Interfaces in the Same I/O Column

To place multiple interfaces in the same I/O column, you must ensure that the global reset signals (global_reset_n, which is an asynchronous reset input to the memory controller and is synchronized internally) for each individual interface all come from the same input pin or signal.

I/O Banks Selection

  • For each memory interface, select adjacent I/O banks. To determine whether I/O banks are adjacent, refer to the I/O Pin Counts tables located in the Arria® 10 Core Fabric and General Purpose I/Os Handbook. You can always assume I/O banks are adjacent within an I/O column except in the following conditions:
    • When an I/O bank is not bonded out on the package (contains the '-' symbol in the I/O table).
    • An I/O bank does not contain 48 pins, indicating that it is only partially bonded out.
  • A memory interface can only span across I/O banks in the same I/O column.
  • Because I/O bank 2A is also employed for configuration-related operations, you can use it to construct external memory interfaces only when the following conditions are met:
    • The pins required for configuration related use (such as configuration bus for Fast Passive Parallel mode or control signals for Partial Reconfiguration) are never shared with pins selected for EMIF use, even after configuration is complete.
    • The I/O voltages are compatible.
    • The design has achieved a successful fit in the Quartus® Prime software.

    Refer to the Arria® 10 Device Handbook and the Configuration Function column of the Pin-Out files for more information about pins and configuration modes.

  • The number of I/O banks that you require depends on the memory interface width.
  • The 3V I/O bank does not support dynamic OCT or calibrated OCT. To place a memory interface in a 3V I/O bank, ensure that calibrated OCT is disabled for the address/command signals, the memory clock signals, and the data bus signals, during IP generation.
  • In some device packages, the number of I/O pins in some LVDS I/O banks is less than 48 pins.

Address/Command Pins Location

  • All address/command pins for a controller must be in a single I/O bank.
  • If your interface uses multiple I/O banks, the address/command pins must use the middle bank. If the number of banks used by the interface is even, any of the two middle I/O banks can be used for address/command pins.
  • Address/command pins and data pins cannot share an I/O lane but can share an I/O bank.
  • The address/command pin locations for the soft and hard memory controllers are predefined. In the External Memory Interface Pin Information for Devices spreadsheet, each index in the "Index within I/O bank" column denotes a dedicated address/command pin function for a given protocol. The index number of the pin specifies to which I/O lane the pin belongs:
    • I/O lane 0—Pins with index 0 to 11
    • I/O lane 1—Pins with index 12 to 23
    • I/O lane 2—Pins with index 24 to 35
    • I/O lane 3—Pins with index 36 to 47
  • For memory topologies and protocols that require only three I/O lanes for the address/command pins, use I/O lanes 0, 1, and 2.
  • Unused address/command pins in an I/O lane can be used as general-purpose I/O pins.

CK Pins Assignment

Assign the clock pin (CK pin) according to the number of I/O banks in an interface:

  • If the number of I/O banks is odd, assign one CK pin to the middle I/O bank.
  • If the number of I/O banks is even, assign the CK pin to either of the middle two I/O banks.

Although the Fitter can automatically select the required I/O banks, Intel® recommends that you make the selection manually to reduce the pre-fit run time.

PLL Reference Clock Pin Placement

Place the PLL reference clock pin in the address/command bank. Other I/O banks may not have free pins that you can use as the PLL reference clock pin:

  • If you are sharing the PLL reference clock pin between several interfaces, the I/O banks must be consecutive.

The Arria® 10 external memory interface IP does not support PLL cascading.

RZQ Pin Placement

You may place the RZQ pin in any I/O bank in an I/O column with the correct VCCIO and VCCPT for the memory interface I/O standard in use. However, the recommended location is in the address/command I/O bank, for greater flexibility during debug if a narrower interface project is required for testing.

DQ and DQS Pins Assignment

Intel® recommends that you assign the DQS pins to the remaining I/O lanes in the I/O banks as required:

  • Constrain the DQ and DQS signals of the same DQS group to the same I/O lane.
  • You cannot constrain DQ signals from two different DQS groups to the same I/O lane.

If you do not specify the DQS pins assignment, the Fitter selects the DQS pins automatically.

Sharing an I/O Bank Across Multiple Interfaces

If you are sharing an I/O bank across multiple external memory interfaces, follow these guidelines:

  • The interfaces must use the same protocol, voltage, data rate, frequency, and PLL reference clock.
  • You cannot use an I/O bank as the address/command bank for more than one interface. The memory controller and sequencer cannot be shared.
  • You cannot share an I/O lane. There is only one DQS input per I/O lane, and an I/O lane can connect to only one memory controller.
Level Two Title