External Memory Interfaces Arria® 10 FPGA IP User Guide
Visible to Intel only — GUID: sio1520884884991
Ixiasoft
Visible to Intel only — GUID: sio1520884884991
Ixiasoft
3.5.1.3. Data Buffer Controller
- Manages the read and write access to the data buffers:
- Provides the data storing pointers to the buffers when the write data is accepted or the read return data arrives.
- Provides the draining pointer when the write data is dispatched to memory or the read data is read out of the buffer and sent back to users.
- Satisfies the required write latency.
- If ECC support is enabled, assists the main control path to perform read-modify-write.
Data reordering is performed with the data buffer controller and the data buffers.
Each I/O bank contains two data buffer controller blocks for the data buffer lanes that are split within each bank. To improve your timing, place the data buffer controller physically close to the I/O lanes.