Visible to Intel only — GUID: sli1537192526576
Ixiasoft
Visible to Intel only — GUID: sli1537192526576
Ixiasoft
7.3.1.2. DIMM Options
Compared to the unbuffered DIMMs (UDIMM), registered and load-reduced DIMMs (RDIMMs and LRDIMMs, respectively) use at least two chip-select signals CS#[1:0] in DDR3 and DDR4 . Both RDIMMs and LRDIMMs require an additional parity signal for address, RAS#, CAS#, and WE# signals. A parity error signal is asserted by the module whenever a parity error is detected.
LRDIMMs expand on the operation of RDIMMs by buffering the DQ/DQS bus. Only one electrical load is presented to the controller regardless of the number of ranks, therefore only one clock enable (CKE) and ODT signal are required for LRDIMMs, regardless of the number of physical ranks. Because the number of physical ranks may exceed the number of physical chip-select signals, DDR3 LRDIMMs provide a feature known as rank multiplication, which aggregates two or four physical ranks into one larger logical rank. Refer to LRDIMM buffer documentation for details on rank multiplication.
Pins | UDIMM Pins (Single Rank) | UDIMM Pins (Dual Rank) | RDIMM Pins (Single Rank) | RDIMM Pins (Dual Rank) | LRDIMM Pins (Dual Rank) | LRDIMM Pins (Quad Rank) |
---|---|---|---|---|---|---|
Data | 72 bit DQ[71:0]= {CB[7:0], DQ[63:0]} |
72 bit DQ[71:0]= {CB[7:0], DQ[63:0]} |
72 bit DQ[71:0]= {CB[7:0], DQ[63:0]} |
72 bit DQ[71:0]= {CB[7:0], DQ[63:0]} |
72 bit DQ[71:0]= {CB[7:0], DQ[63:0]} |
72 bit DQ[71:0]= {CB[7:0], DQ[63:0]} |
Data Mask | DM#/DBI#[8:0] (1) | DM#/DBI#[8:0] (1) | DM#/DBI#[8:0] (1) | DM#/DBI#[8:0] (1) | — | — |
Data Strobe | x8: DQS[8:0] and DQS#[8:0] | x8: DQS[8:0] and DQS#[8:0] | x8: DQS[8:0] and DQS#[8:0] x4: DQS[17:0] and DQS#[17:0] | x8: DQS[8:0] and DQS#[8:0] x4: DQS[17:0] and DQS#[17:0] | x4: DQS[17:0] and DQS#[17:0] | x4: DQS[17:0] and DQS#[17:0] |
Address | BA[1:0], BG[1:0], A[16:0] - 4GB: A[14:0] 8GB: A[15:0] 16GB: A[16:0] (2) |
BA[1:0], BG[1:0], A[16:0] - 8GB: A[14:0] 16GB: A[15:0] 32GB: A[16:0] (2) |
BA[1:0], BG[1:0], x8: A[16:0] - 4GB: A[14:0] 8GB: A[15:0] 16GB: A[16:0] (2) 32GB: A[17:0] (3) |
BA[1:0], BG[1:0],x8: A[16:0] x4: A[17:0] - 8GB: A[14:0] 16GB: A[15:0] 32GB: A[16:0] (2) 64GB: A[17:0] (3) |
BA[1:0], BG[1:0], A[17:0] - 16GB: A[15:0] 32GB: A[16:0] (2) 64GB: A[17:0] (3) |
BA[1:0], BG[1:0], A[17:0] - 32GB: A[15:0] 64GB: A[16:0] (2) 128GB: A[17:0] (3) |
Clock | CK0/CK0# | CK0/CK0#, CK1/CK1# | CK0/CK0# | CK0/CK0# | CK0/CK0# | CK0/CK0# |
Command | ODT, CS#, CKE, ACT#, RAS#/A16, CAS#/A15, WE#/A14 | ODT[1:0], CS#[1:0], CKE[1:0], ACT#, RAS#/A16, CAS#/A15, WE#/A14 | ODT, CS#, CKE, ACT#, RAS#/A16, CAS#/A15, WE#/A14 | ODT[1:0], CS#[1:0], CKE, ACT#, RAS#/A16, CAS#/A15, WE#/A14 | ODT, CS#[1:0], CKE, ACT#, RAS#/A16, CAS#/A15, WE#/A14 | ODT, CS#[3:0], CKE, ACT#, RAS#/A16, CAS#/A15, WE#/A14 |
Parity | PAR, ALERT# | PAR, ALERT# | PAR, ALERT# | PAR, ALERT# | PAR, ALERT# | PAR, ALERT# |
Other Pins | SA[2:0], SDA, SCL, EVENT#, RESET# | SA[2:0], SDA, SCL, EVENT#, RESET# | SA[2:0], SDA, SCL, EVENT#, RESET# | SA[2:0], SDA, SCL, EVENT#, RESET# | SA[2:0], SDA, SCL, EVENT#, RESET# | SA[2:0], SDA, SCL, EVENT#, RESET# |
Notes to Table:
|