Visible to Intel only — GUID: hco1416492487649
Ixiasoft
Visible to Intel only — GUID: hco1416492487649
Ixiasoft
4.2.3. AFI Write Data Signals
Signal Name |
Direction |
Width |
Description |
---|---|---|---|
afi_dqs_burst |
Input |
AFI_RATE_RATIO |
Controls the enable on the strobe (DQS) pins for DDR3 and LPDDR3 memory devices. When this signal is asserted, mem_dqs and mem_dqsn are driven. This signal must be asserted before afi_wdata_valid to implement the write preamble, and must be driven for the correct duration to generate a correctly timed mem_dqs signal. |
afi_wdata_valid |
Input |
AFI_RATE_RATIO |
Write data valid signal. This signal controls the output enable on the data and data mask pins. |
afi_wdata |
Input |
AFI_DQ_WIDTH |
Write data signal to send to the memory device at double-data rate. This signal controls the PHY’s mem_dq output. |
afi_dm |
Input |
AFI_DM_WIDTH |
Data mask. This signal controls the PHY’s mem_dm signal for DDR3 and LPDDR3 memory devices. Also directly controls the PHY's mem_dbi signal for DDR4. The mem_dm and mem_dbi features share the same port on the memory device. |
afi_bws_n |
Input |
AFI_DM_WIDTH |
Data mask. This signal controls the PHY’s mem_bws_n signal for QDR II/II+ memory devices. |
afi_dinv |
Input |
AFI_WRITE_DQS_WIDTH * 2 |
Data inversion. It directly controls the PHY's mem_dinva/b signal for QDR-IV devices. |