Visible to Intel only — GUID: hco1416490817121
Ixiasoft
Visible to Intel only — GUID: hco1416490817121
Ixiasoft
8.3.1.6.5. QDR II, QDR II+ and QDR II+ Xtreme SRAM Data, BWS, and QVLD Signals
At the pin, the read data is edge-aligned with the CQ and CQ# clocks while the write data is center-aligned with the K and K# clocks (see the following figures).
The byte write select signal (BWS#) indicates which byte to write into the memory device.
QDR II+ and QDR II+ Xtreme SRAM devices also have a QVLD pin that indicates valid read data. The QVLD signal is edge-aligned with the echo clock and is asserted high for approximately half a clock cycle before data is output from memory.