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Visible to Intel only — GUID: hco1416491669328
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5.2.6. Simulating the Design Example
To simulate the design example in the Quartus® Prime software using the Cadence simulator, follow these steps:
- At the Linux* shell command prompt, change directory to sim\ed_sim\cadence
- Run the simulation by typing the following command at the command prompt:
sh xcelium_setup.sh
To simulate the example design in the Quartus® Prime software using the Synopsys* simulator, follow these steps:
- At the Linux* shell command prompt, change directory to sim\ed_sim\synopsys\vcsmx
- Run the simulation by typing the following command at the command prompt:
sh vcsmx_setup.sh
To simulate the example design in the Quartus® Prime software using the Siemens EDA simulator, follow these steps:
- At the Linux or Windows shell command prompt, change directory to sim\ed_sim\mentor
- Execute the msim_setup.tcl script that automatically compiles and runs the simulation by typing the following command at the Linux or Windows command prompt:
vsim -do msim_setup.tcl
or
Type the following command at the ModelSim* command prompt:
do msim_setup.tcl
For more information about simulating the external memory interface using the Siemens EDA simulator, refer to the Simulating External Memory Interface IP With ModelSim chapter in the Arria® 10 External Memory Interfaces IP Design Example User Guide .
To simulate the example design in the Quartus® Prime software using the Aldec simulator, follow these steps:
- At the Linux or Windows shell command prompt, change directory to sim\ed_sim\aldec
- Execute the rivierapro_setup.tcl script that automatically compiles and runs the simulation by typing the following command at the Linux or Windows command prompt: vsim -do rivierapro.tcl
- To compile and elaborate the design after the script loads, type ld_debug.
- Type run -all to run the simulation.
For more information about simulation, refer to the Simulating Designs chapter in Volume 3 of the Quartus® Prime Handbook.
If your Quartus® Prime project appears to be configured correctly but the example testbench still fails, check the known issues on the Intel FPGA Knowledge Base before filing a service request.