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Ixiasoft
Visible to Intel only — GUID: hco1416490803935
Ixiasoft
6.3.1.2. DIMM Options
Compared to the unbuffered DIMMs (UDIMM), registered and load-reduced DIMMs (RDIMMs and LRDIMMs, respectively) use at least two chip-select signals CS#[1:0] in DDR3 and DDR4 . Both RDIMMs and LRDIMMs require an additional parity signal for address, RAS#, CAS#, and WE# signals. A parity error signal is asserted by the module whenever a parity error is detected.
LRDIMMs expand on the operation of RDIMMs by buffering the DQ/DQS bus. Only one electrical load is presented to the controller regardless of the number of ranks, therefore only one clock enable (CKE) and ODT signal are required for LRDIMMs, regardless of the number of physical ranks. Because the number of physical ranks may exceed the number of physical chip-select signals, DDR3 LRDIMMs provide a feature known as rank multiplication, which aggregates two or four physical ranks into one larger logical rank. Refer to LRDIMM buffer documentation for details on rank multiplication.
The following table shows UDIMM and RDIMM pin options for DDR3.
Pins |
UDIMM Pins (Single Rank) |
UDIMM Pins (Dual Rank) |
RDIMM Pins (Single Rank) |
RDIMM Pins (Dual Rank) |
---|---|---|---|---|
Data |
72 bit DQ[71:0] = {CB[7:0], DQ[63:0]} |
72 bit DQ[71:0] = {CB[7:0], DQ[63:0]} |
72 bit DQ[71:0] = {CB[7:0], DQ[63:0]} |
72 bit DQ[71:0]= {CB[7:0], DQ[63:0]} |
Data Mask |
DM[8:0] |
DM[8:0] |
DM[8:0] |
DM[8:0] |
Data Strobe |
DQS[8:0] and DQS#[8:0] |
DQS[8:0] and DQS#[8:0] |
DQS[8:0] and DQS#[8:0] |
DQS[8:0] and DQS#[8:0] |
Address |
BA[2:0], A[15:0]– 2 GB: A[13:0] 4 GB: A[14:0] 8 GB: A[15:0] |
BA[2:0], A[15:0]– 2 GB: A[13:0] 4 GB: A[14:0] 8 GB: A[15:0] |
BA[2:0], A[15:0]– 2 GB: A[13:0] 4 GB: A[14:0] 8 GB: A[15:0] |
BA[2:0], A[15:0]– 2 GB: A[13:0] 4 GB: A[14:0] 8 GB: A[15:0] |
Clock |
CK0/CK0# |
CK0/CK0#, CK1/CK1# |
CK0/CK0# |
CK0/CK0# |
Command |
ODT, CS#, CKE, RAS#, CAS#, WE# |
ODT[1:0], CS#[1:0], CKE[1:0], RAS#, CAS#, WE# |
ODT, CS#[1:0], CKE, RAS#, CAS#, WE# 2 |
ODT[1:0], CS#[1:0], CKE[1:0], RAS#, CAS#, WE# |
Parity |
— |
— |
PAR, ALERT |
PAR, ALERT |
Other Pins |
SA[2:0], SDA, SCL, EVENT#, RESET# |
SA[2:0], SDA, SCL, EVENT#, RESET# |
SA[2:0], SDA, SCL, EVENT#, RESET# |
SA[2:0], SDA, SCL, EVENT#, RESET# |
The following table shows LRDIMM pin options for DDR3.
Pins |
LRDIMM Pins (x4, 2R) |
LRDIMM (x4, 4R, RMF=1) 3 |
LRDIMM Pins (x4, 4R, RMF=2) |
LRDIMM Pins (x4, 8R, RMF=2) |
LRDIMM Pins (x4, 8R, RMF=4) |
LRDIMM (x8, 4R, RMF=1) 3 |
LRDIMM Pins (x8, 4R, RMF=2) |
---|---|---|---|---|---|---|---|
Data |
72 bit DQ [71:0]= {CB [7:0], DQ [63:0]} |
72 bit DQ [71:0]= {CB [7:0], DQ [63:0]} |
72 bit DQ [71:0]= {CB [7:0], DQ [63:0]} |
72 bit DQ [71:0]= {CB [7:0], DQ [63:0]} |
72 bit DQ [71:0]= {CB [7:0], DQ [63:0]} |
72 bit DQ [71:0]= {CB [7:0], DQ [63:0]} |
72 bit DQ [71:0]= {CB [7:0], DQ [63:0]} |
Data Mask |
— |
— |
— |
— |
— |
DM[8:0] | DM[8:0] |
Data Strobe |
DQS[17:0] and DQS#[17:0] |
DQS[17:0] and DQS#[17:0] |
DQS[17:0] and DQS#[17:0] |
DQS[17:0] and DQS#[17:0] |
DQS[17:0] and DQS#[17:0] |
DQS[8:0] and DQS#[8:0] | DQS[8:0] and DQS#[8:0] |
Address |
BA[2:0], A[15:0] |
BA[2:0], A[15:0] |
BA[2:0], A[16:0] |
BA[2:0], A[16:0] |
BA[2:0], A[17:0] |
BA[2:0], A[15:0] |
BA[2:0], A[16:0] |
Clock |
CK0/CK0# |
CK0/CK0# |
CK0/CK0# |
CK0/CK0# |
CK0/CK0# |
CK0/CK0# |
CK0/CK0# |
Command |
ODT, CS[1:0]#, CKE, RAS#, CAS#, WE# |
ODT, CS[3:0]#, CKE, RAS#, CAS#, WE# |
ODT, CS[2:0]#, CKE, RAS#, CAS#, WE# |
ODT, CS[3:0]#, CKE, RAS#, CAS#, WE# |
ODT, CS[3:0]#, CKE, RAS#, CAS#, WE# |
ODT, CS[3:0]#, CKE, RAS#, CAS#, WE# |
ODT, CS[2:0]#, CKE, RAS#, CAS#, WE# |
Parity |
PAR, ALERT |
PAR, ALERT |
PAR, ALERT |
PAR, ALERT |
PAR, ALERT |
PAR, ALERT |
PAR, ALERT |
Other Pins |
SA[2:0], SDA, SCL, EVENT#, RESET# |
SA[2:0], SDA, SCL, EVENT#, RESET# |
SA[2:0], SDA, SCL, EVENT#, RESET# |
SA[2:0], SDA, SCL, EVENT#, RESET# |
SA[2:0], SDA, SCL, EVENT#, RESET# |
SA[2:0], SDA, SCL, EVENT#, RESET# |
SA[2:0], SDA, SCL, EVENT#, RESET# |
Notes to Table:
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