Visible to Intel only — GUID: mhi1457030019994
Ixiasoft
Visible to Intel only — GUID: mhi1457030019994
Ixiasoft
4.3.3. AFI Read Sequence Timing Diagrams
The afi_rdata_en_full signal must be asserted for the entire read burst operation. The afi_rdata_en signal need only be asserted for the intended read data.
Aligned and unaligned access for read commands is similar to write commands; however, the afi_rdata_en_full signal must be sent on the same memory clock in a PHY clock as the read command. That is, if a read command is sent on the second memory clock in a PHY clock, afi_rdata_en_full must also be asserted, starting from the second memory clock in a PHY clock.
The following figure illustrates that the second and third reads require only the first and second half of data, respectively. The first three read commands are aligned accesses where they are issued on the LSB of afi_command. The fourth read command is unaligned access, where it is issued on a different command slot. AFI signals must be shifted accordingly, based on command slot.
In the following figure, the first three read commands are aligned accesses where they are issued on the LSB of afi_command. The fourth read command is unaligned access, where it is issued on a different command slot. AFI signals must be shifted accordingly, based on command slot.