Visible to Intel only — GUID: hco1416492485138
Ixiasoft
Visible to Intel only — GUID: hco1416492485138
Ixiasoft
4.2.2. AFI Address and Command Signals
Signal Name |
Direction |
Width |
Description |
---|---|---|---|
afi_addr |
Input |
AFI_ADDR_WIDTH |
Address or CA bus (LPDDR3 only). ADDR_RATE_RATIO is 2 for LPDDR3 CA bus. |
afi_bg |
Input |
AFI_BANKGROUP_WIDTH |
Bank group (DDR4 only). |
afi_ba |
Input |
AFI_BANKADDR_WIDTH |
Bank address. (Not applicable for LPDDR3.) |
afi_cke |
Input |
AFI_CLK_EN_WIDTH |
Clock enable. |
afi_cs_n |
Input |
AFI_CS_WIDTH |
Chip select signal. (The number of chip selects may not match the number of ranks; for example, RDIMMs and LRDIMMs require a minimum of 2 chip select signals for both single-rank and dual-rank configurations. Consult your memory device data sheet for information about chip select signal width.) (Matches the number of ranks for LPDDR3.) |
afi_ras_n |
Input |
AFI_CONTROL_WIDTH |
RAS# (for DDR3 memory devices.) |
afi_we_n |
Input |
AFI_CONTROL_WIDTH |
WE# (for DDR3 memory devices.) |
afi_rw_n |
Input |
AFI_CONTROL_WIDTH * 2 |
RWA/B# (QDR-IV). |
afi_cas_n |
Input |
AFI_CONTROL_WIDTH |
CAS# (for DDR3 memory devices.) |
afi_act_n |
Input |
AFI_CONTROL_WIDTH |
ACT# (DDR4). |
afi_rst_n |
Input |
AFI_CONTROL_WIDTH |
RESET# (for DDR3 and DDR4 memory devices.) |
afi_odt |
Input |
AFI_CLK_EN_WIDTH |
On-die termination signal for DDR3, and LPDDR3 memory devices. (Do not confuse this memory device signal with the FPGA’s internal on-chip termination signal.) |
afi_par |
Input |
AFI_CS_WIDTH |
Address and command parity input. (DDR4) Address parity input. (QDR-IV) |
afi_ainv |
Input |
AFI_CONTROL_WIDTH |
Address inversion. (QDR-IV) |
afi_mem_clk_disable |
Input |
AFI_CLK_PAIR_COUNT |
When this signal is asserted, mem_clk and mem_clk_n are disabled. This signal is used in low-power mode. |
afi_wps_n |
Output |
AFI_CS_WIDTH |
WPS (for QDR II/II+ memory devices.) |
afi_rps_n |
Output |
AFI_CS_WIDTH |
RPS (for QDR II/II+ memory devices.) |