Visible to Intel only — GUID: arw1504106465992
Ixiasoft
Visible to Intel only — GUID: arw1504106465992
Ixiasoft
2. External Memory Interfaces Arria® 10 FPGA IP Introduction
You can easily implement the EMIF IP core functions through the Quartus® Prime software. The Quartus® Prime software also provides external memory toolkits that help you test the implementation of the IP in the FPGA.
The External Memory Interfaces Arria® 10 FPGA IP (referred to hereafter as the Arria® 10 EMIF IP) provides the following components:
- A physical layer interface (PHY) which builds the data path and manages timing transfers between the FPGA and the memory device.
- A memory controller which implements all the memory commands and protocol-level requirements.
For information on the maximum speeds supported by the external memory interface IP, refer to the External Memory Interface Spec Estimator.
Arria® 10 Protocol and Feature Support
- Supports DDR4, DDR3, and LPDDR3 protocols with hard memory controller and hard PHY.
- Supports QDR-IV, QDR II + Xtreme, QDR II +, and QDR II using soft memory controller and hard PHY.
- Supports RLDRAM 3 using third-party soft controller.
- Supports Ping Pong PHY mode, allowing two memory controllers to share command, address, and control pins.
- Supports error correction code (ECC) for both hard memory controller and soft memory controller.