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1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example
8. Achieving Timing Closure on a Motor Control Design
9. Design Security Recommendations
10. Reference Documents for the Drive-on-Chip Design Example
11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3.1. Software Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
3.3. Downloading and Installing the Design
3.4. Setting Up the Motor Control Board with your Development Board for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
3.5. Importing the Drive-On-Chip Design Example Software Project
3.6. Configuring the FPGA Hardware for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
3.7. Programming the Nios II Software to the Device for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
3.8. Applying Power to the Power Board
3.9. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
3.10. System Console GUI Upper Pane for the Drive-On-Chip Design Example
3.11. System Console GUI Lower Pane for the Drive-On-Chip Design Example
3.12. Controlling the DC-DC Converter
3.13. Tuning the PI Controller Gains
3.14. Controlling the Speed and Position Demonstrations
3.15. Monitoring Performance
4.1. Changing the Intel® MAX® 10 ADC Thresholds or Conversion Sequence
4.2. Generating the Qsys System
4.3. Compiling the Hardware in the Intel Quartus Prime Software
4.4. Generating and Building the Nios II BSP for the Drive-On-Chip Design Example
4.5. Software Application Configuration Files
4.6. Compiling the Software Application for the Drive-On-Chip Design Example
4.7. Programming the Design into Flash Memory
7.1. Processor Subsystem
7.2. Six-channel PWM Interface
7.3. DC Link Monitor
7.4. Drive System Monitor
7.5. Quadrature Encoder Interface
7.6. Sigma-Delta ADC Interface for Drive Axes
7.7. Intel® MAX® 10 ADCs
7.8. ADC Threshold Sink
7.9. DC-DC Converter
7.10. Motor Control Modes
7.11. FOC Subsystem
7.12. DEKF Technique
7.13. Signals
7.14. Registers
7.11.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs
7.11.2. Avalon Memory-Mapped Interface
7.11.3. About DSP Builder for Intel FPGAs
7.11.4. DSP Builder for Intel FPGAs Folding
7.11.5. DSP Builder for Intel FPGAs Model Resource Usage
7.11.6. DSP Builder for Intel FPGAs Design Guidelines
7.11.7. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
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7.2. Six-channel PWM Interface
The Drive-on-Chip Design Example six-channel PWM interface operates as three pairs of outputs, with each driving the upper and lower power transistors (e.g., MOSFET driven via external drivers) in a half-bridge power stage.
The PWM interface operates with a PWM carrier clock of 300 MHz for high resolution control of the MOSFET switching times.
The PWM interface ensures a dead time between switching to ensure both outputs are not high at the same time; the dead time prevents short circuit “shoot-through” in the power transistors. The input clock and a PWM counter set the PWM frequency. The counter alternately ramps up from zero to a maximum value and ramps down from the maximum value to zero. The sequence is as follows:
0, 1, 2, …, max - 1, max, max - 1, …, 2, 1, 0, …
Figure 25. PWM Counter Value
The maximum value of the counter ramp, max, is software configurable. The PWM frequency is fPWM = fCLK/(2 x max). The 16-bit counter resolution is sufficient to generate an 8, 16, or 32 kHz PWM output.
The design generates high- and low-side drive signals for the MOSFET module by comparing the ramp counter value with the values you set in the PWM threshold configuration registers. The design inserts a dead period between the switching of the upper and lower drive signals according to the value set in the PWM blocking time configuration register.
The design sets carrier_latch output signal high for one clock cycle when the PWM counter is at 0 or max. This signal triggers a position encoder to take a position reading.
The start output signal is a trigger for the ADC IP to start conversion. The trigger_up configuration register sets the PWM count value and the start signal is high for one clock cycle while the PWM is counting up. The trigger_down configuration register sets the PWM count value and the start signal is high for one clock cycle while the PWM is counting down. Set the trigger_up and trigger_down registers symmetrically to ensure a regular ADC sample position offset before the reversal point of the counter. In other words, trigger_up = MAX - offset, and trigger_down = offset.
The design calculates the PWM blocking time configuration register as pwm_block = dead time x fCLK. Dead time refers to the time when the design turns off both upper and lower transistors, to prevent short circuits. You must obtain specific dead time values for the specific MOSFET module you are using. For example, with a dead time requirement of 2μs and a PWM module clock of 300 MHz, the pwm_block value is 600 (=2μs x 300 MHz. Figure 5 shows PWM output generation (including dead time).
Figure 26. PWM Output Generation (Including Dead Time)
Based on the PWM counter value, the PWM component generates configurable timing output strobes for triggering ADC conversion for feedback-current readings. Configure the ADC start pulse to perform the conversion during the quietest period of the PWM cycle away from PWM switching events (around the min and max values of the PWM counter).
Figure 27. Configurable Timing Output Strobes