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1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example
8. Achieving Timing Closure on a Motor Control Design
9. Design Security Recommendations
10. Reference Documents for the Drive-on-Chip Design Example
11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3.1. Software Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
3.3. Downloading and Installing the Design
3.4. Setting Up the Motor Control Board with your Development Board for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
3.5. Importing the Drive-On-Chip Design Example Software Project
3.6. Configuring the FPGA Hardware for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
3.7. Programming the Nios II Software to the Device for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
3.8. Applying Power to the Power Board
3.9. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
3.10. System Console GUI Upper Pane for the Drive-On-Chip Design Example
3.11. System Console GUI Lower Pane for the Drive-On-Chip Design Example
3.12. Controlling the DC-DC Converter
3.13. Tuning the PI Controller Gains
3.14. Controlling the Speed and Position Demonstrations
3.15. Monitoring Performance
4.1. Changing the Intel® MAX® 10 ADC Thresholds or Conversion Sequence
4.2. Generating the Qsys System
4.3. Compiling the Hardware in the Intel Quartus Prime Software
4.4. Generating and Building the Nios II BSP for the Drive-On-Chip Design Example
4.5. Software Application Configuration Files
4.6. Compiling the Software Application for the Drive-On-Chip Design Example
4.7. Programming the Design into Flash Memory
7.1. Processor Subsystem
7.2. Six-channel PWM Interface
7.3. DC Link Monitor
7.4. Drive System Monitor
7.5. Quadrature Encoder Interface
7.6. Sigma-Delta ADC Interface for Drive Axes
7.7. Intel® MAX® 10 ADCs
7.8. ADC Threshold Sink
7.9. DC-DC Converter
7.10. Motor Control Modes
7.11. FOC Subsystem
7.12. DEKF Technique
7.13. Signals
7.14. Registers
7.11.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs
7.11.2. Avalon Memory-Mapped Interface
7.11.3. About DSP Builder for Intel FPGAs
7.11.4. DSP Builder for Intel FPGAs Folding
7.11.5. DSP Builder for Intel FPGAs Model Resource Usage
7.11.6. DSP Builder for Intel FPGAs Design Guidelines
7.11.7. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
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4.5. Software Application Configuration Files
You can modify the operation of the software application for the Drive-On-Chip Design Example by editing some C source code and header files.
File | Path | Function |
---|---|---|
demo_cfg.c | . | Declare motors[] Array |
demo_cfg.h | . | Configuration macros and include file for demo_cfg.c |
motor_types.c | Platform/motors | Declares motor types and encoders |
motor_types.h | Platform/motors | Defines motor and encoder types and include file for motor_types.c |
Macro | Default State | Range | Function |
---|---|---|---|
FIRST_MULTI_AXIS | 0 | 0 - 1 | Index of first motor axis to be controlled. |
LAST_MULTI_AXIS | 1 | 0 - 1 | Index of last motor axis to be controlled. |
DEFAULT_ADC_TYPE | ADC_TYPE_SIGMA_DELTA | ADC_TYPE_SIGMA_DELTA | Use sigma delta ADC samples in control loop. |
ADC_TYPE_MAX10 | Use MAX10 ADC samples in control loop. | ||
SD_ADC_FILTER
|
ADC_D_10US | ADC_D_10US | Sinc3 filter delay 10 us. |
ADC_D_50US | Sinc3 filter delay 50 us. | ||
DC_LINK_STARTUP_TARGET_VOLTS | 32 | 12 - 48 | Target voltage for DC-DC converter. |
OPEN_LOOP_INIT
|
0 | 0 | Start motors in closed loop mode. |
1 | Start motors in open loop mode. | ||
INTERACTIVE_START |
0 | 0 | Normal startup 1: |
1 | User prompted via Nios II console at each stage of startup | ||
ENCODER_SERVICE
|
Undefined | Undefined | Normal operation. |
DBG_DEFAULT
|
DBG_INFO
|
DBG_NEVER | No console output. |
DBG_ALWAYS | Always output. | ||
DBG_FATAL | Debug level set to fatal errors . | ||
DBG_ERROR | Debug level set to non-fatal errors and above . | ||
DBG_WARN | Debug level set to warnings and above . | ||
DBG_INFO | Debug level set to information and above . | ||
DBG_PERF | Debug level set to performance data and above . | ||
DBG_DEBUG | Debug level set to debug messages and above . | ||
DBG_DEBUG_MORE | Debug level set to more debug messages and above . | ||
DBG_ALL | Debug level set to all messages. |