Visible to Intel only — GUID: hco1433528007894
Ixiasoft
Visible to Intel only — GUID: hco1433528007894
Ixiasoft
7.11.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs
The FOC algorithm comprises the FOC algorithm block and a latch block for implementing the integrators necessary for the PI controllers in the FOC algorithm. DSP Builder for Intel FPGAs implements the latches outside because of limitations of the folding synthesis.
The design includes fixed-point and floating-point models that implement the FOC algorithm. Only the fixed-point model has the SVM block. The design performs the SVM calculation in software for the floating-point models.
Each model calls a corresponding .m setup script during initialization to set up the arithmetic precision, folding factor, and target clock speed. The folding factor is set to a large value to minimize resource usage.
Model | Folding Factor | Clock Speed (MHz) | Input Precision | Output Precision |
---|---|---|---|---|
Fixed point | 500 | 100 | sfix16En10 | sfix32En10 |
Floating point | 500 | 100 | sfix32En10 | sfix32En10 |
The following models generate the FOC block including the Avalon memory-mapped interface:
- DFf_float_alu_av.slx for floating-point designs
- DFf_fixp16_alu_av.slx for fixed-point designs
Verification models stimulate the FOC algorithm using dynamically changing inputs:
- verify_DF_float_alu.slx
- verify_DF_fixp16_alu.slx
Closed-loop simulation models validate that the FOC correctly controls a motor in simulation:
- sim_DF_float_alu.slx
- sim_DF_fixp16_alu.slx
A Simulink library model contains the main FOC algorithm code, which the other models refer to:
- foc_blocks.slx