AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

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ID 683072
Date 7/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices 3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example 8. Achieving Timing Closure on a Motor Control Design 9. Design Security Recommendations 10. Reference Documents for the Drive-on-Chip Design Example 11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.1. Software Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up the Motor Control Board with your Development Board for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.5. Importing the Drive-On-Chip Design Example Software Project 3.6. Configuring the FPGA Hardware for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.7. Programming the Nios II Software to the Device for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.8. Applying Power to the Power Board 3.9. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 3.10. System Console GUI Upper Pane for the Drive-On-Chip Design Example 3.11. System Console GUI Lower Pane for the Drive-On-Chip Design Example 3.12. Controlling the DC-DC Converter 3.13. Tuning the PI Controller Gains 3.14. Controlling the Speed and Position Demonstrations 3.15. Monitoring Performance
3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.2.1. Preparing the Rechargeable Battery
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
4.1. Changing the Intel® MAX® 10 ADC Thresholds or Conversion Sequence 4.2. Generating the Qsys System 4.3. Compiling the Hardware in the Intel Quartus Prime Software 4.4. Generating and Building the Nios II BSP for the Drive-On-Chip Design Example 4.5. Software Application Configuration Files 4.6. Compiling the Software Application for the Drive-On-Chip Design Example 4.7. Programming the Design into Flash Memory
4.5. Software Application Configuration Files x
4.5.1. Defining a New Motor or Encoder Type
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta and MAX 10 Integrated ADCs 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the System Console Toolkit
6. Motor Control Software x
6.1. Viewing Motor Control Software Help Files
7. Functional Description of the Drive-on-Chip Design Example x
7.1. Processor Subsystem 7.2. Six-channel PWM Interface 7.3. DC Link Monitor 7.4. Drive System Monitor 7.5. Quadrature Encoder Interface 7.6. Sigma-Delta ADC Interface for Drive Axes 7.7. Intel® MAX® 10 ADCs 7.8. ADC Threshold Sink 7.9. DC-DC Converter 7.10. Motor Control Modes 7.11. FOC Subsystem 7.12. DEKF Technique 7.13. Signals 7.14. Registers
7.4. Drive System Monitor x
7.4.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.6. Sigma-Delta ADC Interface for Drive Axes x
7.6.1. Offset Adjustment for Sigma-Delta ADC Interface
7.9. DC-DC Converter x
7.9.1. DC-DC Control Simulink Models 7.9.2. Sigma-Delta ADC Interface for DC-DC Converter
7.9.1. DC-DC Control Simulink Models x
7.9.1.1. DC-DC Control Block 7.9.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
7.9.1.1. DC-DC Control Block x
7.9.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
7.11. FOC Subsystem x
7.11.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.11.2. Avalon Memory-Mapped Interface 7.11.3. About DSP Builder for Intel FPGAs 7.11.4. DSP Builder for Intel FPGAs Folding 7.11.5. DSP Builder for Intel FPGAs Model Resource Usage 7.11.6. DSP Builder for Intel FPGAs Design Guidelines 7.11.7. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
8. Achieving Timing Closure on a Motor Control Design x
8.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example
8. Achieving Timing Closure on a Motor Control Design
9. Design Security Recommendations
10. Reference Documents for the Drive-on-Chip Design Example
11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices

7.10. Motor Control Modes

The Drive-on-Chip Design Example supports various control algorithms and commutation modes.
The design supports:
  • Open-loop Volts/Hz speed control with sinusoidal commutation
  • Speed and position control with field-oriented current control (FOC), sinusoidal commutation with quadrature encoder or resolver feedback.
  • Sensorless speed control with field-oriented current control using a sliding-mode speed and position observer using current feedback
  • Speed control with trapezoidal commutation using Hall sensor feedback

Open Loop

The design supports open loop control using sinusoidal commutation and trapezoidal commutation. The design uses Volts per Hz control in which the voltage the design applies to the motor increases with increasing frequency (motor speed). After each interrupt the interrupt service routine (ISR) updates a ramp generator to represent the motor electrical angle based on the previous angle, desired speed, and sample rate. The ISR calculates the voltage to apply using a Volts per Hz control gain based on the frequency and motor parameters. In open loop sinusoidal commutation, the ISR applies the inverse Park Transform and SVM function from FOC to generate sinusoidal commutation.
Figure 35. Open Loop Sinusoidal Commutation

FOC with Position Sensor Feedback

The design supports FOC sensor control where the motor position feeds back to form a closed loop with position and speed PI control. The design senses the motor position by incremental (quadrature) encoders.

The design samples and uses the motor phase currents as feedback to the FOC algorithm.
Figure 36. FOC with Position Sensor Feedback

High-speed FOC with Position Sensor Feedback

The high-speed FOC sensor mode closely resembles the standard FOC with position sensor feedback mode, but operates at 64 kHz instead of 16 or 32 kHz. In this mode, the design performs the FOC calculation only with the FOC DSP Builder IP. Phase currents U and W are directly connected to the sigma-delta ADC interface. The output space vector modulation PWM values are directly connected to the six-channel PWM interface.

The ADC interface operates at 64 kHz and is synchronized with the PWM to eliminate FET switching noise from the power board.

Figure 37. Block diagram for high-speed FOC connection

The figure shows the high-speed FOC connection. In the diagram, bold lines represent the Avalon interface, single lines indicate the direct interface, and blue lines indicate one item triggers the next. ISR uses interface IP and algorithm acceleration IPs for control and diagnostics. The ISR calls Avalon memory-mapped interfaces

Figure 38. Timing diagram for high-speed FOC The figure shows the timing diagram for the high-speed FOC. Although the software operates at 32 kHz, the FOC DSP IP receives input and output updates at a frequency of 64 kHz.

PWM counter values reaching PWM_TRIGGER_UP and PWM_TRIGGER_DOWN initiate ADC conversion for feedback-current readings. When the ADC reading stabilizes, the latch_en signal is set to high. The avs_irq signal activates each ISR service routine, determined by the irq_counter and latch_en. The irq_counter value ensures sufficient time for each ISR service routine and is automatically calculated in the software based on the FOC running speed.

Table 14.  High-speed FOC Signals (RTL)
Signal Name (RTL) Signal Location

latch_en

irq_counter

ip/ssg_emb_sd_adc/ssg_emb_sd_adc.v and ip/ssg_emb_sd_adc/ssg_emb_sd_adc_diff.v

avs_irq

irq_ack

Ip/ssg_emb_sd_adc/ssg_emb_sd_adc.v
Table 15.  High-speed FOC Signals (Software)
Signal Name (Software) Description
adc_irq_ack

Set adc_irq_ack to 1 to acknowledge the interrupt request received.

Set adc_irq_ack to 0 to turn on the system to handle interrupt requests.

Functions are in doc_adc.c and used in motor_task.c

FOC Sensorless

The design supports FOC sensorless control in which the design samples and uses both the motor phase voltages and currents as the feedback to the control loop.

The phase voltage calc block derives signals Vα and Vβ, scaled and normalized with respect to the DC bus voltage (Vdclink). The DC bus voltage may drop during quick acceleration or rise during regeneration. If you do not expect the bus voltage to change much (e.g. large bus capacitance), you may use Vα and Vβ generated from the inverse Clarke transform. The software function Phase_Volt_Calc_f() implements the phase voltage calculations using floating-point arithmetic.

The design integrates the speed estimator with the sliding mode observer (SMO) to allow a second order observer to calculate both estimated angle and estimated speed together. In FOC sensorless mode, the motor starts initially in open loop with a requested speed and switches to sensorless mode after a preset time to allow the SMO to settle. The software function SMO_Calc_f() implements the SMO calculations using floating-point arithmetic.

Figure 39. FOC Sensorless Control

Sliding Mode Observer Theory

Figure 40. SMO_Calc_f() software function

The observer, based on the electrical model, estimates the rotating back-EMF vector. The rotor position determines the direction of the back-EMF, which enables estimation of position. At constant speed, back-EMF components are sinusoidal in quadrature, as are error signals. Considering voltage V and current I in one motor phase with resistance Rs, inductance Ls. Net applied voltage V is at the motor terminal, and the centre of the motor is at 0 V.

Solving the differential equation for i, assuming a constant v applied over sample time T, initial current i, and current at the end of T i + 1, gives:

Normalizing by some V max and I max to create variables that are non-dimensional and always <1, gives:

Aparm is non-dimensional, represents the electrical system dynamics. Ls/Rs is the electrical time constant, Ts is the discrete sample time. Aparm should be close to 1 if the sample time is much faster than the motor time constant.

Bparm uses Vmax/(Imax*Rs) so is also nondimensional. (1-Aparm) is small.

Aparm and Bparm are constant and are calculated once during initialization of the software.

Angle Tracking Observer Theory

The angle tracking observer (part of SMO_Calc_f()) takes the estimated back-EMF vector as input and outputs an estimated rotor position (phi_SMO). The back-EMF estimate may be noisy so the observer filters it and converts it to position. The design provides two methods:

  1. #if (TRACKER_ENABLE == 0), arctan method: A first order filter with gain Lpf_Gain is applied to both alpha and beta components of the back-EMF before using arctan to convert them to phi_SMO. The advantage is simplicity, but velocity must be estimated separately. The design does not use this method as the speed estimation may introduce lag.
  2. Angle observer method: The design combines the back-EMF estimates with the last phi_SMO to calculate AObsError, which is proportional to speed*sin(actual-estimate). Assuming small errors and constant speed, AobsError=K*(θElec - phi_SMO). Phi_SMO has units of fraction of 1rev (0..1 for 0..2π rad).
Figure 41. Angle Tracking ObserverInduced voltage ve = d/dt(φ) = Rotor back-EMF in q-direction in FOC. Rotor electrical angle θelec = direction of magnetic flux vector φ = d-direction in FOC.

The back-EMF operates in the q-direction,, which is at right-angles to the d-direction (θelec_rad). The components of the back-EMF in the fixed alpha and beta directions are:

  • vBemfAlpha_V = -dθmech_dt_rad_s*Ke_Vs_rad*sin(θelec_rad)
  • vBemfBeta_V = dθmech_dt_rad_s*Ke_Vs_rad*cos(θelec_rad)
  • AobsError is the back-EMF in the estimated d direction (phi_SMO), which is zero if phi_SMO is equal to θelec_rad
  • AObsError = -vBemfAlpha_V*cos(phi_SMO)-vBemfBeta_V*sin(phi_SMO)

Substituting the Bemf equations into the AObsError equation:

AObsError = dθmech_dt_rad_s*Ke_Vs_rad*( sin(θelec_rad)*cos(phi_SMO)-cos(θelec_rad)*sin(phi_SMO) )

= dθmech_dt_rad_s*Ke_Vs_rad*sin(θelec_rad - phi_SMO)

Hence, if the BemfAlpha and BemfBeta values are correct, AObsError measures the angle estimation error (θelec_rad - phi_SMO).

For small error angles and at constant speed, assume AObsError = K*(θelec - phi_SMO)

AObsError = K(θk- φk)

The software creates a second-order filter from θelec to phi_SMO. Filter natural frequency Ω and damping coefficient ζ are design parameters tuned for the Tamagawa motors in the Tandem Motion-Power 48 V motor kit. The normalized scaling makes them suitable for other motors too with possible retuning. Carefully tune this non-linear observer because incorrect position estimates can make the FoC algorithm oscillate or become unstable by causing positive feedback.

Figure 42. Feedback System

SMO Parameters

The design derives various SMO parameters from the motor parameters for each motor type, such as resistance and inductance. Other SMO parameters, and default values, are:

Table 16.  SMO Parameters
Parameter Description
Lpf_Gain = 0.10

Arctan method of angle calculation only. The final two stages of the SMO are a low-pass filter on each component of the estimated BEMF followed by an inverse tangent (arctan observer). The output of the inverse tangent is the estimated angle. The parameter Lpf_Gain sets the cutoff frequency of the low-pass filter.

Lpf_Gain = 2*pi*fc*Ts

where: Ts is the sample period and fc is the desired cutoff frequency.

damping_coefficient = 1.4

These are both parameters of the angle tracking observer, which takes in both unfiltered components of the estimated BEMF, extracts the angle and filters in one module. The angle tracking observer has no speed dependent phase lag, unlike the arctan observer. Setting natural_frequency too low can result in instability in the speed estimation.

natural_frequency = 600

Hys_Gain = 0.8

This parameter sets the sliding mode gain on the current observer. This observer is responsible for estimating the BEMF signals that it ultimately feeds into the angle tracking observer. To adjust this parameter, run the motor and view the estimated angle waveform. If it looks like an undistorted triangle no adjustment should be necessary. If the triangle looks distorted, while running at constant speed, adjust this parameter to clean it up.

Trapezoidal

The design supports trapezoidal control of BLDC motors using Hall sensor feedback on the Tandem Motion-Power 48 V Board. The software supports Duty Mode and Torque Mode, but the demonstration GUI only uses Velocity Mode. The software reconstructs the motor current from the individual phase current readings using the Hall encoder state to determine which phase current is relevant.

Figure 43. Trapezoidal Commutation Using Hall Sensor Feedback
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