Intel® C++ Compiler Classic Developer Guide and Reference

ID 767249
Date 3/31/2023
Public

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svrng_generate[1|2|4|8|16|32]_[uint|ulong]

Generates uniform random bits over the a specified range

Syntax

uint32_t svrng_generate_uint( svrng_engine_t engine )

svrng_uint1_t svrng_generate1_uint( svrng_engine_t engine )

svrng_uint2_t svrng_generate2_uint( svrng_engine_t engine )

svrng_uint4_t svrng_generate4_uint( svrng_engine_t engine )

svrng_uint8_t svrng_generate8_uint( svrng_engine_t engine )

svrng_uint16_t svrng_generate16_uint( svrng_engine_t engine )

svrng_uint32_t svrng_generate32_uint( svrng_engine_t engine )

uint64_t svrng_generate_ulong( svrng_engine_t engine )

svrng_ulong1_t svrng_generate1_ulong( svrng_engine_t engine )

svrng_ulong2_t svrng_generate2_ulong( svrng_engine_t engine )

svrng_ulong4_t svrng_generate4_ulong( svrng_engine_t engine )

svrng_ulong8_t svrng_generate8_ulong( svrng_engine_t engine )

svrng_ulong16_t svrng_generate16_ulong( svrng_engine_t engine )

svrng_ulong32_t svrng_generate32_ulong( svrng_engine_t engine )

Input Parameters

engine

Pointer to the engine.

Description

The svrng_generate[n]_[uint|ulong] functions generate uniform random bits over the range [0, MAX) with engine-dependent maximum value. The uint versions are available for 32-bit engines only ( rand0, rand, mcg31m1, mt19937 ), the ulong versions are available for 64-bit engines only ( mcg59 ). The number n if specified expresses the number of packed unsigned integer elements in returned SIMD registers.

Status flags set

Name

Description

SVRNG_STATUS_ERROR_UNSUPPORTED

Unmatched engine and result type. See the Description section for supported combinations.

SVRNG_STATUS_ERROR_BAD_ENGINE

Bad engine (NULL pointer)

Return Values

Unsigned integer random value(s). The svrng_generate_[uint|ulong] functions return a single unsigned 32- or 64-bit integer random value. The svrng_generate[n]_[uint|ulong] functions, for n=1, 2, 4, 8, 16, or 32 return as many unsigned, 32- or 64-bit integer random values packed in a SIMD register.