External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

7. Agilex™ 5 FPGA EMIF IP - DDR5 Support

This chapter contains IP parameter descriptions and pin planning information for Agilex™ 5 FPGA external memory interface IP for DDR5.