External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide

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ID 683162
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 4. External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide Archives 5. Document Revision History for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Generating the Synthesizable EMIF Design Example 2.4. Generating the EMIF Design Example for Simulation 2.5. Simulation Versus Hardware Implementation 2.6. Simulating External Memory Interface IP With ModelSim 2.7. Pin Placement for Intel® Agilex™ 7 F-Series and I-Series EMIF IP 2.8. Compiling and Programming the Intel® Agilex™ 7 F-Series and I-Series EMIF Design Example 2.9. Generating a Design Example with the Calibration Debug Option 2.10. Generating a Design Example with the TG Configuration Option 2.11. Using the Design Example with the EMIF Debug Toolkit
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel® Agilex™ 7 F-Series and I-Series EMIF Parameter Editor Guidelines
2.10. Generating a Design Example with the TG Configuration Option x
2.10.1. Enabling the Traffic Generator in a Design Example
3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Designs Interface Tab
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
4. External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide Archives
5. Document Revision History for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide

2.4. Generating the EMIF Design Example for Simulation

For the Intel® Agilex™ 7 F-Series and I-Series development kit, it is sufficient to leave most of the Intel® Agilex™ 7 F-Series and I-Series EMIF IP settings at their default values. To generate the design example for simulation, follow these steps:
  1. On the Example Designs tab, ensure that the Simulation box is checked. Also choose the required Simulation HDL format, either Verilog or VHDL.
  2. Configure the EMIF IP and click File > Save to save the current setting into the user IP variation file (<user instance name>.ip).
  3. Click Generate Example Design in the upper-right corner of the window.

  4. Specify a directory for the EMIF design example and click OK. Successful generation of the EMIF design example creates multiple file sets for various supported simulators, under a sim/ed_sim directory.
  5. Click File > Exit to exit the IP Parameter Editor Pro window. The system prompts, Recent changes have not been generated. Generate now? Click No to continue with the next flow.
    Figure 5. Generated Simulation Design Example File Structure
    Note: The External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP currently supports only the VCS, ModelSim/QuestaSim, and Xcelium simulators. Additional simulator support is planned in future releases.
Note:

If you don't select the Simulation or Synthesis checkbox, the destination directory contains only Platform Designer design files, which are not compilable by the Intel® Quartus® Prime software directly, but which you can view or edit in the Platform Designer. In this situation you can run the following commands to generate synthesis and simulation file sets.

  • To create a compilable project, you must run the 
    quartus_sh -t make_qii_design.tcl
    script in the destination directory.
  • To create a simulation project, you must run the
    quartus_sh -t make_sim_design.tcl
    script in the destination directory.
Note: If you have generated a design example and then make changes to it in the parameter editor, you must regenerate the design example to see your changes implemented. The newly generated design example does not overwrite the existing design example files.
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