DisplayPort IP Support Center

1. Device and IP Selection

What features are supported in the DisplayPort IP?

Note: The High-bandwidth Digital Content Protection (HDCP) feature is not included in the Intel Quartus Prime Pro Edition software. For more information goto HDCP feature at Media Connectivity Solutions - Intel® FPGAs.

Which Intel® FPGA Device Family Should I Use?

Link Rate Supported by Device Family

The table below shows the resource information for Arria V and Cyclone V devices using M10K; Intel Arria 10, Intel Stratix 10, and Stratix V devices using M20K.

The resources were obtained using the following parameter settings:

• Mode = simplex
• Maximum lane count = 4 lanes
• Maximum video input color depth = 8 bits per color (bpc)
• Pixel input mode = 1 pixel per clock

Note: Conditional support for Intel Agilex 7, Intel Arria 10 and Intel Stratix 10 FPGA Fabric Speed Grade 3. Contact your sales representative for more information.

What is the DisplayPort Intel FPGA IP Core FPGA Resource Utilization?

Performance and Resource Utilization

The resource utilization data indicates typical expected performance for the DisplayPort Intel FPGA IP.

The below table lists the resources and expected performance for selected variations. The results were obtained using the Intel Quartus Prime Pro Edition software version 20.2 for the following devices:

• Intel Agilex® F-tile (AGIB027R31B1E2VR0)
• Intel Stratix 10 (1SG280HU1F50E2VGS1)
• Intel Arria 10 (10AX115S2F45I1SG)
• Intel Cyclone 10 GX (10CX220YF780E5G)

DisplayPort 1.4 Intel FPGA IP Resource Utilization

The table below shows the resource information for Intel Agilex 7, Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 devices using M20K. The resources were obtained using the following parameter settings:

• Mode = simplex
• Maximum lane count = 4 lanes
• Maximum video input color depth = 8 bits per color (bpc)
• Pixel input mode = 1 pixel per clock, 4 pixel per clock for Intel Agilex 7

DisplayPort 2.0 Intel FPGA IP Resource Utilization

The table below shows the resource information for Intel Stratix 10 devices using the M20K. The resource count for the DP2.0 includes the resource count for the DP1.4 as well. The resources were obtained using the following parameter settings:

• Mode = simplex
• Maximum lane count = 4 lanes
• Maximum video input color depth = 8 bits per color (bpc)
• Pixel input mode = 4 pixel per clock

HDCP Resource Utilization

The table lists the HDCP resource data for DisplayPort Intel FPGA IP with configurations of SST (single stream) and at maximum lane of 4 configuration for Intel Arria 10 and Intel Stratix 10 devices.

2. Design Flow and IP Integration

What is the DisplayPort related information and documentation available?

Intel® Agilex® 7 (F-tile), Intel® Stratix® 10 (H-tile and L-tile), Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria V GX/GT/GS, Arria V GZ, Cyclone V, Stratix V

• DisplayPort Intel® FPGA IP User Guide

How do I generate the DisplayPort IP core?

Steps to generate DisplayPort IP Core in the Intel Quartus Prime software can be found in the chapter for Specifying IP Parameters and Options.

• DisplayPort Intel® FPGA IP User Guide

What is supported in the Intel Quartus generated DisplayPort design example?

The DisplayPort Intel FPGA IP core design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module. The below table illustrates design example options available for Intel Agilex 7, Intel Stratix 10, Intel Arria 10 and Intel Cyclone 10 GX devices.

How do I generate the Intel Quartus DisplayPort design example?

For Intel Agilex® 7, Intel Stratix, Intel Arria 10, and Intel Cyclone 10 GX devices, use the DisplayPort Intel FPGA parameter editor in the Intel Quartus Prime Pro Edition software to generate the design example.

• Click Tools > IP Catalog, and select target device family.
• In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP. The New IP Variation window appears.
• Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named ip.
• You may select a specific FPGA device in the Device field, or keep the default Intel Quartus Prime software device selection.
• Click OK. The parameter editor appears.
• Configure the desired parameters for both TX and RX.
• On the Design Example tab, select the design example that fits your criteria.
• Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example. You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
• For Target Development Kit, select the available Intel FPGA development kit. If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit.
• Click Generate Example Design.

Similarly, the links below provides step-by-step instruction to generate

DisplayPort design example from the Intel Quartus Prime software:

• DisplayPort Intel Agilex® 7 F-Tile FPGA IP Design Example User Guide
• DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
• DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide
• DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

How do I compile and test my design?

For Intel Agilex 7 and 10-series devices, the steps to compile and test your DisplayPort design can be found in the following DisplayPort Design

Compiling and Testing the Design:

• DisplayPort Intel Agilex® 7 F-Tile FPGA IP Design Example User Guide
• DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
• DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide
• DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

How can I perform DisplayPort functional simulation?

For Intel Agilex 7, Intel Stratix, Intel Arria 10, and Intel Cyclone 10 GX devices, below are the steps to generate DisplayPort functional simulation:

Enable the simulation option in the DisplayPort Parameter Editor and generate DisplayPort design example.

Simulating Design:

• DisplayPort Intel Agilex® 7 F-Tile FPGA IP Design Example User Guide
• DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
• DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide
• DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

Simulation Testbench:

• DisplayPort Intel Agilex® 7 F-Tile FPGA IP Design Example User Guide
• DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
• DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide
• DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

Where do I find information on the Clock Recovery Core?

The Intel Agilex 7, Intel Stratix, Intel Arria 10, and Intel Cyclone 10 GX DisplayPort design example uses Pixel Clock Recovery IP.

Clock Recovery Core information:

• Intel® DisplayPort IP Core User Guide

Where do I find information on the DisplayPort Link Training flow?

Before the source device can send video data to sink device, a Link Training process has to be completed between source-sink.

DisplayPort Link Training Flow:

• Intel DisplayPort IP Core User Guide

Where do I find information on the DisplayPort API reference and DPCD information?

The following resources will provide instructions for the DisplayPort application programming interface (API) reference and DPCD:

• Source-supported DPCD locations
• Sink-supported DPCD locations
• DisplayPort Intel® FPGA IP User Guide
  

3. Board Design and Power Management

Pin Connection Guidelines

Intel Agilex 7 Devices

• Intel Agilex® 7 Device Family Pin Connection Guidelines

Intel Stratix 10 Devices

• Intel Stratix 10 GX, MX, TX and SX Device Family Pin Connection Guidelines

Intel Arria 10 Devices

• Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines

Intel Cyclone 10 GX Devices

• Intel Cyclone 10 GX Device Family Pin Connection Guidelines

Schematic Review

Intel Agilex 7 Devices

• Intel Agilex® 7 Schematic Review Worksheet

Intel Stratix 10 Devices

• Intel Stratix 10 GX, MX, and SX Schematic Review Worksheet
• Intel Stratix 10 GX FPGA Development Kit User Guides and Schematics
• Intel Stratix 10 SX SoC Development Kit User Guides and Schematics

Intel Arria 10 Devices

• Intel Arria 10 GX, GT, and SX Schematic Review Worksheet
• Intel Arria 10 GX FPGA Development Kit User Guides and Schematics
• Intel Arria 10 SoC Development Kit User Guides and Schematics

Intel Cyclone GX 10 Devices

• Intel Cyclone 10 GX Schematic Review Worksheet
• Intel Cyclone 10 GX FPGA Development Kit User Guides and Schematics

Board Design Guidelines

• AN 958: Board Design Guidelines Solutions
• Board Layout Test
• AN 114: Board Design Guidelines for Intel® Programmable Device Packages
• AN 766: Intel Stratix 10 Devices, High-Speed Signal Interface Layout Design Guideline
• AN 613: PCB Stackup Design Considerations for Intel FPGAs
• AN745: Design Guideline for Intel FPGA DisplayPort Interface
• FMC DisplayPort Daughter Card Revision 8 Schematics
• FMC DisplayPort Daughter Card Revision 11 Schematics
• HSMC DisplayPort 1.2 Daughter Card Schematics

Disclaimer: The Intel Arria 10 and Intel Stratix 10 Development Kit on-board DisplayPort TX board design implementation is NOT recommended as it does not allow PMA + PCS bonding. Users are advised to refer to the Bitec design implementation.

Power Management

• Early Power Estimator (EPE) and Power Analyzer
• AN 750: Using the Intel FPGA PDN Tool to Optimize Your Power Delivery Network Design
• Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide
• Early Power Estimator for Intel® Cyclone® 10 GX FPGAs User Guide
• Early Power Estimator for Intel® Arria® 10 FPGAs User Guide
• AN 711: Power Reduction Features in Intel® Arria® 10 Devices
• AN 721: Creating an FPGA Power Tree
• AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Devices
• Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide
• Intel® Stratix® 10 Power Management User Guide
• Intel® Agilex® 7 Power Management User Guide
• AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines
• Intel® Quartus® Prime Pro Edition User Guide Power Analysis and Optimization
• Intel® FPGA Power and Thermal Calculator User Guide

Thermal Power Management

Intel Stratix 10 Devices

• AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
• AN 943: Thermal Modeling for Intel Stratix 10 FPGAs with the Intel FPGA Power and Thermal Calculator
• AN 944: Thermal Modeling for Intel Agilex® 7 FPGAs with the Intel® FPGA Power and Thermal Calculator

Power Sequencing

Intel Stratix 10, Intel Cyclone 10 GX, and Intel Arria 10 Devices

• AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, Intel Stratix 10 and Intel Agilex® 7 Devices

My design require Bitec FMC daughter card. How do I select them?

The following table provides a quick guideline in selecting Bitec FMC daughtercard revision.

Any requirement to use single or dual lanes transceiver channel with Bitec FMC daughter card for 10-series devices?

Yes. For DisplayPort design that uses/referred to in an early version of Bitec FMC daughtercard (revision 9 and earlier), the pin assignment in the following link has to be followed at TX and RX due to the lane reversal and polarity inversion at the channel.

How do I create a DisplayPort TX-only or RX-only design?

A general guideline to create a DisplayPort TX-only or RX-only design can be found in the DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide. Alternatively, a more detailed explanation specific to the DisplayPort TX-only design can be referred to in the AN 883: Intel Arria 10 DisplayPort TX-only Design User Guide.

4. Design Examples

Intel Arria 10 Devices

• AN 793: Intel Arria 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design
• Intel Arria 10 DisplayPort TX-only Design User Guide
• Intel Arria 10 DisplayPort Design Example using On-board Connector (TX-Only)
• DisplayPort UHD Scaler and Mixer Design Example User Guide
• AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design.
• AN 889: 8K DisplayPort Video Format Conversion Design Example

5. Debug

How do I debug my DisplayPort design?

Monitor link training completion status, link rate, and channel count on the development kit on-board user LED.

• DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

Monitor video Main Stream Attributes (MSA) information and auxiliary channel traffic of link training via Nios II terminal.

• DisplayPort Intel® FPGA IP User Guide
• AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

Calculate the required video resolution bandwidth and its recovered clock.

• Intel DisplayPort Bandwidth & PCR Calculator

Translate DisplayPort Link Training AUX Transaction

• Intel® DisplayPort Link Training AUX Translation Tool