System_Mgr Address Map

System Manager core registers

Module Instance	Base Address	End Address
`i_sys_mgr_core`	`0xFFD12000`	`0xFFD124FF`

Register	Offset	Width	Access	Reset Value	Description
`siliconid1`	`0x0`	`32`	`RO`	`0x00020001`	Silicon ID1 Register
`siliconid2`	`0x4`	`32`	`RO`	`0x00000000`	Silicon ID2 Register
`wddbg`	`0x8`	`32`	`RW`	`0x08080808`	L4 Watchdog Debug Register
`mpu_status`	`0x10`	`32`	`RO`	`0x00000000`	This is MPU control register
`mpu_ace`	`0x14`	`32`	`RW`	`0x00000202`	This is MPU control register
`dma`	`0x20`	`32`	`RW`	`0x00000000`	Control Register
`dma_periph`	`0x24`	`32`	`RW`	`0x00000000`	Peripheral Security Register
`sdmmc`	`0x28`	`32`	`RW`	`0x00000000`	Control Register
`sdmmc_l3master`	`0x2C`	`32`	`RW`	`0x00000301`	SD/MMC L3 Master HPROT Register
`nand_bootstrap`	`0x30`	`32`	`RW`	`0x00000000`	Bootstrap Control Register
`nand_l3master`	`0x34`	`32`	`RW`	`0x00003300`	NAND L3 Master AxCACHE Register
`usb0_l3master`	`0x38`	`32`	`RW`	`0x00003001`	USB L3 Master HPROT AHB-Lite Register
`usb1_l3master`	`0x3C`	`32`	`RW`	`0x00003001`	USB L3 Master HPROT AHB-Lite Register
`emac_global`	`0x40`	`32`	`RW`	`0x00000000`	EMAC L3 Master AxCACHE Register
`emac0`	`0x44`	`32`	`RW`	`0x12000003`	Control Register
`emac1`	`0x48`	`32`	`RW`	`0x12000003`	Control Register
`emac2`	`0x4C`	`32`	`RW`	`0x12000003`	Control Register
`emac0_ace`	`0x50`	`32`	`RW`	`0x00000033`	The EMAC0 ACE-lite control register
`emac1_ace`	`0x54`	`32`	`RW`	`0x00000033`	The EMAC1 ACE-lite control register
`emac2_ace`	`0x58`	`32`	`RW`	`0x00000033`	The EMAC2 ACE-lite control register
`nand_axuser`	`0x5C`	`32`	`RW`	`0x00000000`	The NAND ACE-lite contrl a(w/r)user register
`fpgaintf_en_1`	`0x68`	`32`	`RW`	`0x01010110`	FPGA interface Individual Enable Register
`fpgaintf_en_2`	`0x6C`	`32`	`RW`	`0x00000000`	FPGA interface Individual Enable Register
`fpgaintf_en_3`	`0x70`	`32`	`RW`	`0x00000000`	FPGA interface Individual Enable Register
`dma_l3master`	`0x74`	`32`	`RW`	`0x0000F000`	Register for ACE-lite control - dma_l3master
`etr_l3master`	`0x78`	`32`	`RW`	`0x0000F000`	Register for ACE-lite control - etr_l3master
`sec_ctrl_slt`	`0x80`	`32`	`RO`	`0x00000001`	This is the clock selection register. The APS oscillator selection is read only register. This value is driven from secure manager FS.
`osc_trim`	`0x84`	`32`	`RO`	`0x00000000`	This is the osc_trim register to show internal oscillator
`ecc_intmask_value`	`0x90`	`32`	`RW`	`0x00000000`	ECC interrupt mask register. This is a read/write register.
`ecc_intmask_set`	`0x94`	`32`	`WO`	`0x00000000`	ECC interrupt mask Set register
`ecc_intmask_clr`	`0x98`	`32`	`WO`	`0x00000000`	ECC interrupt mask Clear register
`ecc_intstatus_serr`	`0x9C`	`32`	`RO`	`0x00000000`	ECC single bit error status of individual modules. A write to this register should return an error.
`ecc_intstatus_derr`	`0xA0`	`32`	`RO`	`0x00000000`	ECC double bit error status of individual modules. A write to this register should return an error.
`noc_addr_remap`	`0xB0`	`32`	`RW`	`0x00000000`	The noc_addr_repmap register to view the HPS memory map (specifically on-chip RAM)
`hmc_clk`	`0xB4`	`32`	`RO`	`0x0`	HMC Clock and IO Lock status indicator
`io_pa_ctrl`	`0xB8`	`32`	`RW`	`0x00000007`	HMC clock status indicator
`noc_timeout`	`0xC0`	`32`	`RW`	`0x00000000`
`noc_idlereq_set`	`0xC4`	`32`	`WO`	`0x00000000`	Set IDLE request to each NOC master.
`noc_idlereq_clr`	`0xC8`	`32`	`WO`	`0x00000000`	Clear IDLE request to each NOC master.
`noc_idlereq_value`	`0xCC`	`32`	`WO`	`0x00000000`	IDLE request to each NOC master. This register can be set by writing 1 to the specific bit in noc_idlereq_set register. This register can be cleared by writing 1 to the specific bit in noc_idlereq_clr register
`noc_idleack`	`0xD0`	`32`	`RO`	`0x00000011`	Idle acknowledge value from NOC Masters. This is asserted (value 1 in the field) in response to the IDLE requests asserted by software.
`noc_idlestatus`	`0xD4`	`32`	`RO`	`0x00000011`	Status of IDLE from the NOC masters. A 1 in the field means the specific master is idle.
`fpga2soc_ctrl`	`0xD8`	`32`	`RW`	`0x00000001`
`fpga_config`	`0xDC`	`32`	`RO`	`0x00000000`	FPGA configuration read only register
`iocsrclk_gate`	`0xE0`	`32`	`RW`	`0x00000000`	IO Clock control
`gpo`	`0xE4`	`32`	`RW`	`0x00000000`	Provides a low-latency, low-performance, and simple way to drive general-purpose signals to the FPGA fabric
`gpi`	`0xE8`	`32`	`RO`	`0x00000000`	Provides a low-latency, low-performance, and simple way to read general-purpose signals driven from the FPGA fabric.
`mpu`	`0xF0`	`32`	`RW`	`0x00000000`	Provides a low-latency, low-performance, and simple way to read general-purpose signals driven from the FPGA fabric.
`sdm_hps_spare`	`0xF4`	`32`	`RW`	`0x00000000`	SDM to HPS spare signals are mapped to a system manager register. PSI side band signals will set these bits and HPS SW will clear this register
`hps_sdm_spare`	`0xF8`	`32`	`RW`	`0x00000000`	HPS to SDM spare signals are mapped to a system manager register.
`boot_scratch_cold0`	`0x200`	`32`	`RW`	`0x00000000`	Boot scratch register 0
`boot_scratch_cold1`	`0x204`	`32`	`RW`	`0x00000000`	Boot scratch register 1
`boot_scratch_cold2`	`0x208`	`32`	`RW`	`0x00000000`	Boot scratch register 2
`boot_scratch_cold3`	`0x20C`	`32`	`RW`	`0x00000000`	Boot scratch register 3
`boot_scratch_cold4`	`0x210`	`32`	`RW`	`0x00000000`	Boot scratch register 4
`boot_scratch_cold5`	`0x214`	`32`	`RW`	`0x00000000`	Boot scratch register 5
`boot_scratch_cold6`	`0x218`	`32`	`RW`	`0x00000000`	Boot scratch register 6
`boot_scratch_cold7`	`0x21C`	`32`	`RW`	`0x00000000`	Boot scratch register 7
`boot_scratch_cold8`	`0x220`	`32`	`RW`	`0x00000000`	Boot scratch register 8
`boot_scratch_cold9`	`0x224`	`32`	`RW`	`0x00000000`	Boot scratch register 9